• ETRI Journal
• /
• v.39 no.4
• /
• pp.570-581
• /
• 2017

Multiplication in finite fields is used in many applications, especially in cryptography. It is a basic and the most computationally intensive operation from among all such operations. Several systolic multipliers are proposed in the literature that offer low hardware complexity or high speed. In this paper, a bit-parallel polynomial basis systolic multiplier for generic irreducible polynomials is proposed based on a modified interleaved multiplication method. The hardware complexity and delay of the proposed multiplier are estimated, and a comparison with the corresponding multipliers available in the literature is presented. Of the corresponding multipliers, the proposed multiplier achieves a reduction in the hardware complexity of up to 20% when compared to the best multiplier for m = 163. The synthesis results of application-specific integrated circuit and field-programmable gate array implementations of the proposed multiplier are also presented. From the synthesis results, it is inferred that the proposed multiplier achieves low power consumption and low area complexitywhen compared to the best of the corresponding multipliers.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.4
• /
• pp.477-483
• /
• 2015

The k-Winners-Take-All (kWTA) is an operation to find the largest k (>1) inputs among N inputs. Parallel search algorithm of kWTA for digital inputs is not invented yet, so most of digital kWTA architectures have O(N) time complexity. A parallel search algorithm for digital kWTA operation and the circuits for its VLSI implementation are presented in this paper. The proposed kWTA architecture can compare all inputs simultaneously in parallel. The time complexity of the new architecture is O(logN), so that it is scalable to a large number of digital data. The high-speed kWTA operation and its O(logN) dependency of the new architecture are verified by simulations. It takes 290 ns in searching for 5 winners among 1024 of 32 bit data, which is more than thousands of times faster than existing digital kWTA circuits, as well as existing analog kWTA circuits.

• Proceedings of the IEEK Conference
• /
• 2002.07b
• /
• pp.971-974
• /
• 2002

Petri net is an effective modeling tool for concurrent systems. Liveness problem is one of analysis problems in Petri net theory verifying whether the system is free from any local deadlocks. It is well known that computational complexity of liveness problem of general Petri net is deterministic exponential space. Some subclasses, such as marked graph and free choice net, are suggested where liveness problem is verified in less complexity. This paper studies liveness of siphon containing circuit (SCC) net. Liveness condition based on algebraic inequalities is shown. Then polynomial time decidability of liveness of SCC net is derived, if the given net is known to be an SCC net a priori.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.18 no.5
• /
• pp.30-34
• /
• 1981

This paper deals with the testability evaluation method for the digital systems. This method uses two factors: the complexity and the accessibility. The complexity depends on the ratio in combinational and sequential circuits, number of input/output terminals, and the circuit count by using the gate input level method. The accessibility is how easily to handle the data from I/O terminals. The system testability has a normalized value. Thus, analyzing the testability evaluation, and redesigning the circuit to improve testability, the systems increase interests for the maintenance and have high reliability. Finally, in comparison with Stephenson and Grason's technique, this technique gives sufficiently accurate results for much less computation effort.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.24 no.4
• /
• pp.286-293
• /
• 2019

This study compares and analyzes online update techniques, which estimate the parameters of battery equivalent circuit models in real time. Online update techniques, which are based on extended Kalman filter and recursive least square methods, are constructed by considering the dynamic characteristics of batteries. The performance of the online update techniques is verified by simulation and experiments. Each online update technique is compared and analyzed in terms of complexity and accuracy to propose a suitable guide for selecting algorithms on various types of battery applications.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.23 no.3
• /
• pp.309-316
• /
• 1986

A concatenated coding system using a binary code as the inner code and a nonbinary code as the outer code has been constructed for the purpose of error correction. The complexity of a conventional coding system grows exponentially as the code length of a block code becomes longer. To reduce the complexity for ling code, an effective communication system has been proposed by cascading two codes-binary and norbinary codes. Using a parallel-to-serial circuit and a serial-to-parallel circuit, the concatenated coding system has been designed and constructed by empolying a (7,3) burst error correcting code as the inner code and a (7,3) Reed-Solomon code as the outer code. This system has been simulated and tested using a micro-computer. For the (49,9) concatenated coding system, the error probability of the channel has been evaluated and compared to different coding systems.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.5
• /
• pp.51-60
• /
• 2004

Due to the improvements in circuit design and manufacturing technique, the complexity of a circuit is growing. Since the complexity of a circuit causes high frequency of faults, it is very important to locate faults for improvement of yield and reduction of production cost. But unfortunately it takes a long time to find sites of defects by e-beam proving if the physical level. A fault diagnosis algorithm in the Sate level has meaning to reduce diagnosis time by limiting fault sites. In this paper, we propose an efficient fault diagnosis algorithm in the logical level. Our method is hybrid fault diagnosis algorithm using a new fault dictionary and additional fault simulation which minimizes memory consumption and simulation time.

• Journal of Korea Society of Industrial Information Systems
• /
• v.19 no.6
• /
• pp.1-6
• /
• 2014

The delay-insensitive Null Convention Logic (NCL) asynchronous design as one of innovative asynchronous logic design methodologies has many advantages of inherent robustness, power consumption, and easy design reuses. However, transistor-level structures of conventional NCL gate cells have weakness of low speed, high area overhead or high wire complexity. Therefore, this paper proposes a new high-speed NCL gate cells designed at transistor level for high-speed, low area overhead, and low wire complexity. The proposed NCL gate cells have been compared to the conventional NCL gates in terms of circuit delay, area and power consumption.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.15 no.6
• /
• pp.52-65
• /
• 1978

Computer-aided design of color TV circuits has been tried using circuit analysis programs. Due to the complexity of colorplexed composite video signals of the color TV, conventional methods are difficult to apply in the color TV circuit design. This paper describes how to design Y video circuit, chroma cicruit, AGC circuit, and sync separator circuit of color TV using analysis programs.

• Journal of information and communication convergence engineering
• /
• v.10 no.2
• /
• pp.194-199
• /
• 2012

This paper proposes a novel scheme of a gray scale fingerprint image for a high-accuracy capacitive sensor chip. The conventional grayscale image scheme uses a digital-to-analog converter (DAC) of a large-scale layout or charge-pump circuit with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit for the charge sharing scheme is proposed, which uses a down literal circuit (DLC) with a floating-gate metal-oxide semiconductor transistor (FGMOS) based on a neuron model. The detection circuit is designed and simulated in a 3.3 V, 0.35 ${\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, the pixel layout size can be reduced and the image resolution can be improved.