• Proceedings of the KIEE Conference
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• 2009.04b
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• pp.156-160
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• 2009

This paper presents the interleaved active-clamping ZVS(Zero Voltage Switching) forward converter, which is mainly composed of two active-clamping forward converters. Only two switches are required, and each one is the auxiliary switch for the other. The circuit complexity and cost are thus reduced. The leakage inductance of the transformer or an additional resonant inductance is employed to achieve ZVS during the dead times. The duty cycles are not limited to be equal and within 50%. The complementary switching and the resulted interleaved output inductor currents diminish the current ripple in output capacitors. Accordingly, the smaller output chokes and capacitors lower the converter volume and increase the power density. Detailed analysis and design of this new interleaved active-clamping forward converter are described.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.1
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• pp.34-40
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• 2012

Flux linkage of phase windings or phase inductance is an important parameter in determining the behavior of a switched reluctance motor (SRM) [1-8]. Therefore, the accurate prediction of inductance at aligned and unaligned rotor positions makes a significant contribution to the design of an SRM and its analytical approach is not straightforward due to nonlinear flux distribution. Although several different approaches using a finite element analysis (FEA) or curve-fitting tool have been employed to compute phase inductance [2-5], they are not suitable for a simple design procedure because the FEA necessitates a large amount of time in both modeling and solving with complexity for every motor design, and the curve-fitting requires the data of flux linkage from either an experimental test or an FEA simulation. In this paper, phase inductance at aligned and unaligned rotor positions is estimated by means of numerical method and magnetic equivalent circuit as well, and the proposed approach is analytically verified in terms of the accuracy of estimated inductance compared to inductance computed by an FEA simulation.

• Journal of Magnetics
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• v.18 no.1
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• pp.57-64
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• 2013

Flux linkage of phase windings is a key parameter in determining the behavior of a switched reluctance motor (SRM) [1-8]. Therefore, the accurate prediction of flux linkage at aligned and unaligned rotor positions makes a significant contribution to the design of an SRM and its analytical approach is not straightforward due to nonlinear saturation in flux. Although several different approaches using a finite element analysis (FEA) or a curve-fitting tool have been employed to compute phase flux linkage [2-5], they are not suitable for a simple design procedure because the FEA necessitates a large amount of time in both modeling and solving with complexity for every motor design, and the curve-fitting requires the data of flux linkage from either an experimental test or an FEA simulation. In this paper, phase flux linkage at aligned and unaligned rotor positions is estimated by means of a reluctance network, and the proposed approach is analytically verified in terms of accuracy compared to FEA.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.139-141
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• 2019

Capacitive power transfer has an advantage in the simplicity of the energy link structure. So, the conventional phase -shift full bridge sometime is not always the best choice because of its complexity and high cost. On the other hand, the link capacitance is usually very low and requires high-frequency operation, but, the series resonant converter loses zero-voltage switching feature in the light load condition, which makes the switching loss high especially in CPT system. The paper proposes a new low-cost topology based on asymmetric half-bridge to achieve simplicity as well as wide zero voltage switching range. The design procedure is presented, and circuit operations are analyzed and verified by simulation.

• Journal of IKEEE
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• v.13 no.2
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• pp.118-125
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• 2009

With recent advancement of high-speed, multi-gigabit data transmission capabilities, transmitters usually send data without clock signals for reduction of hardware complexity, power consumption, and cost. Therefore clock and data recovery circuits(CDR) become important to recover the clock and data signals and have been widely studied. This paper presents the design of 10Gbps CDR in 0.18$\mu$m CMOS process. A quarter-rate bang-bang phase detector is designed to reduce the power and circuit complexity, and a 4-stage LC-type VCO is used to improve the jitter characteristics. Simulation results show that the designed CDR consumes 80mW from a 1.8V supply, and exhibits a peak-to-peak jitter of 2.2ps in the recovered clock. The chip layout area excluding pads is 1.26mm$\times$1.05mm.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.5
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• pp.827-834
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• 2020

In this paper, a third-order harmonic mixer is designed using frequency multiplier theory for the microwave airborne radar. Unlike the basic mixer design method, the gate bias voltage, at which the third-harmonic component of the Local frequency (LO) is the maximum, is selected using a frequency multiplier theory to maximize the third-harmonic mixing component at the intermediate frequency (IF). The proposed harmonic mixer was designed and manufactured using a commercial GaAs MESFET device in a plastic package, and it was possible to improve the high conversion loss, circuit complexity, high cost, and manufacturing complexity of the existing microwave mixer. The harmonic mixer using the proposed design method has a -8 ~ -10 dB conversion loss by pumping 11.5 GHz LO with a +5 dBm level when operating from 33.0 GHz to 36.0 GHz and the 1-dB gain compression point (P1dB) of 0 dBm.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.12
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• pp.1337-1344
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• 2014

The objective of an echo canceller connected to any end of a communication line such as digital subscriber line (DSL) is to compensate the outgoing transmit signal in the receiving path that the hybrid circuit leaks. The echo canceller working in a full duplex environment is an adaptive system driven by the local signal. Conventional echo canceller that implement the least mean square (LMS) algorithm provides a low computational burden but poor convergence properties. The length of the echo canceller will directly affect both the degree of performance and the convergence speed of the adaptation process. To cancel long time-varying echoes, the number of tap coefficients of a conventional echo canceller must be large, which decreases the convergence speed of the adaptive filter. This paper proposes an alternative technique for the echo cancellation in a telecommunication channel. The new technique employs the bi-directional least mean square (LMS) algorithm for adaptively computing the optimal set of the coefficients of the echo canceller, which is composed of weighted combination of both feedforward and feedback algorithms. Finally, Simulation results as well as mathematical analysis demonstrates that the proposed echo canceller has faster convergence speed than the conventional LMS echo canceller with nearly equivalent complexity of computation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8C
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• pp.806-815
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• 2006

It is studied to design a low pass filter of the SRC(sample rate converter), which is used to change the sampling rate of digital signals such as in digital modulation and demodulation systems. The larger the conversion ratio of the sample rate becomes, the more signal processing is needed for the filter, which corresponds to the more complexity in circuit realization. Thus it is important to reduce the amount of signal processing for the case of high conversion ratio. In this paper it is presented a design method of a two-stage cascaded FIR filter, which proved to have reduced amount of signal processing in comparison with a conventional single-stage one. The reduction effect of signal processing turned out to be more noticeable for larger value of conversion ratio, for instance, giving down to 72% in complexity for the conversion ratio of 32. It has been shown that the reduction effect is dependent to specific combination of conversion ratios of the cascaded filters. So an exhaustive search has been performed in order to obtain the optimal combination for various values of the total conversion ratio. In this paper every filter is considered to be implemented in the form of a polyphase FIR filter, and its coefficients are determined by use of the Parks-McCllelan algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.10A
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• pp.809-815
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• 2011

In this paper, we have proposed and implemented a novel architecture which can be used to effectively design the modified Euclidean (ME) algorithm for key equation solver (KES) block in high-speed Reed-Solomon (RS) decoder. With polynomial expressions of newly-defined state variables for controlling each processing element (PE), the proposed architecture has simple input/output signals and requires less hardware complexity because no degree computation circuits are needed. In addition, since each PE circuit is independent of the error correcting capability t of RS codes, it has the advantage of linearly increase of the hardware complexity of KES block as t increases. For comparisons, KES block for RS(255,239,8) decoder is implemented using Verilog HDL and synthesized with 0.13um CMOS cell library. From the results, we can see that the proposed architecture can be used for a high-speed RS decoder with less gate count.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.1A
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• pp.27-33
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• 2009

This paper proposes transmit power control techniques with fading channel prediction scheme based on recurrent neural network for high-speed mobile communication systems. The operation result of recurrent neural network which is derived interpretively solves complexity problems of neural network circuit, and channel gain of multiple transmit antenna is derived with maximum ratio combining(MRC) by using the operation result, and this channel gain control transmit power of each antenna. simulation results show that proposed method has a outstanding performance compared to method that is not to be controlled power based on channel prediction. Most of legacy studies are for robust receive technique of fading signals or channel prediction of fading signals limited low-speed mobility, but in open loop Power control, proposed channel prediction method decrease system complexity with removal of fading effect in transmitter.