• Journal of Institute of Control, Robotics and Systems
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• v.1 no.1
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• pp.50-57
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• 1995

In this paper, the design and the implementation of the controller for an articulate robot, which is developed in our Automatic Control Laboratory, are mainly discussed. The controller reduces software computational load via distributed processing method using multiple CPU's, and simplifies structures by the time-division control with TMS320C31 DSP chip. The method of control is based on the fuzzy-compensated PID control with scale factor, which compensates for the influence of load variation resulting from the various postures of the robot with conventional PID scheme. The application of the proposed controller to the robot system with DC servo-motors shows some excellent control capabilities. Also, the response characteristics of system for the various trajectory commands verify the superiority of the controller.

• ETRI Journal
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• v.32 no.4
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• pp.520-529
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• 2010

In this paper, we present a low-voltage low-dropout voltage regulator (LDO) for a system-on-chip (SoC) application which, exploiting the multiplication of the Miller effect through the use of a current amplifier, is frequency compensated up to 1-nF capacitive load. The topology and the strategy adopted to design the LDO and the related compensation frequency network are described in detail. The LDO works with a supply voltage as low as 1.2 V and provides a maximum load current of 50 mA with a drop-out voltage of 200 mV: the total integrated compensation capacitance is about 40 pF. Measurement results as well as comparison with other SoC LDOs demonstrate the advantage of the proposed topology.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.11 no.4
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• pp.147-153
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• 2012

The demands of the large scale machine tools, for instance, such as planomiller, turning machine, boring machine, NC machine, have been gradually increased in recent years. As the performances of machine tools and/or cutting tools are advanced, it is possible to perform high-speed and high-precision cutting works. The effective treatment of wet chip, which is discharged from cutting works, becomes very important problems. Therefore, this study is forced on the design of large scale machine tools using CATIA V5R18 and analysis of cutter, which is considered as essential equipment in large scale machine tools, using MSC.Nastran & MSC.Patran. Especially, the relations between tolerated load of cutter, driving horse power and rpm of driving shaft in chip processing system are investigated through analysis. As the results, the reliability of design could be improved by evaluating simulated numerical values, it showed that tolerated loads of supported part and edged part of cutter are 87,000N and 14,450N, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.404-407
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• 2011

This paper presents a design of current mode PWM/PFM DC-DC Boost converter. This DC-DC Boost Converter operates with PWM mode at the heavy loads and with PFM mode at light loads. The DC-DC boost converter is designed with CMOS 0.35${\mu}m$ technology. It operates at 500KHz and can drive a load current up to 600mA. It has a maximum power efficiency of 92.1%. The total chip area is $1300{\mu}m{\times}1070{\mu}m$ including pads. The DC-DC boost converter operates in a wide range of load currents while occupying a small chip area.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.5
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• pp.94-103
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• 1997

It is necesary that analog buffer circuit should drive an external load in the VLSI design such as switched capacitor efilter (SCF), D/A converter, A/d converter, telecommunicatin circuit, etc. The conventional CMOS buffer circuit have many probvlems according as CMOS technique. Firstly, Capacity of large load ar enot able to opeate well. The problem can be solve to use class AB stages. But large load are operated a difficult, because an element of existing CMOS has a quadratic functional relation with inptu and outut voltage versus output current. Secondly, whole circuit of dynamic rang edecrease, because a range of inpt and output voltages go down according as increasing of intergration rate drop supply voltage. In this paper suggests that new differential CMOS line driver make out of operating an external of large load. In telecommunication's chip case transmission line could be a load. It is necessary that a load operate line driver. The proposal circuit is planned to hav ea high generation power rnage of voltage with preservin linearity. And circuit of capability is inspected through simulation program (HSPICE).

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.11a
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• pp.138-140
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• 2001

Fluxless flip chip bonding using plasma & ultrasonic wave was investigated in order to evaluate the effect of plasma & ultrasonic treatment on the bondability of the Sn-3.5wt%Ag solder bumped die to TSM-coated glass substrate. The $Ar+10%H_2plasma$ was effective in removing tin oxide on solder surface. The die shear strength of the plasma-treated Si-chip is higher than that of non-treated specimen but lower than that of specimen bonded with flux. The die shear strength with the bonding load at 25W ultrasonic power increased to 0.8N/bump for all bonding temperature but decreased above 1.0N/bump.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.85-95
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• 2015

Network-on-chip (NoC) has evolved to overcome the issues of traditional bus-based on-chip interconnect. In NoC-reuse as TAM, the test schedulers are constrained with the topological position of cores and test access points, which may negatively affect the test time. This paper presents a scalable hybrid test data transportation scheme that allows to simultaneously test multiple heterogeneous cores of NoC-based SoCs, while reusing NoC as TAM. In the proposed test scheme, single test stimuli set of multiple CUTs is embedded into each flit of the test stimuli packets and those packets are multicast to the targeted CUTs. However, the test response packets of each CUT are unicast towards the tester. To reduce network load, a flit is filled with maximum possible test response sets before unicasting towards the tester. With the aid of Verilog and analytical simulations, the proposed scheme is proved effective and the results are compared with some recent techniques.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.7 no.2
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• pp.91-99
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• 1998

This paper presents a methodology for identifying the cutter runout geometry in end milling process. Cutter runout is common but undesirable phenomenon in multi-tooth machining because it introduces variable chip loading to insert which results in a accelerated tool wear. amplification of force variation and hence enlargement vibration amplitude From understanding of chip load change kinematics, the analytical cutting force convolution model was formulated as the angular domain convolution model was formulated as the angular domain convolution of three dynamic cutting force component functions. By virtue of the convolution integration property, the frequency domain expression of the local cutting forces and the chip width density of the cutter. Experimental study is presented to validate the analytical model. This study provides the in-process monitoring and compensation of dynamic cutter runout to improve machining tolerance and surface quality for industrial application.

• Journal of the Korean Society for Precision Engineering
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• v.31 no.5
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• pp.395-401
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• 2014

Development of five axis tool grinding machine and CAD/CAM systems increase tool design flexibility. In this research, investigated are cutting characteristics of ball-end mill with different helix angle. Special WC ball-end mills with $0^{\circ}$, $10^{\circ}$, $20^{\circ}$, $30^{\circ}$ helix angles are designed and used in various cutting tests. Machining performance according to helix angle variation is evaluated from cutting forces, surface roughness, tool wear, produced chip shape, and vibration characteristics. The ball-end mill with $10^{\circ}$ helix angle shows the best cutting performance due to appropriate chip load distribution and smooth chip flow. This research can be used for cutting edge geometry optimization and novel design of ball-end mill.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.4
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• pp.176-181
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• 2001

As the data rate between chip-to-chip gets high, the skin effect and load of pins deteriorate noise margin. With these, noise disturbances on the bus channel make it difficult for receiver circuits to read the data signal. This paper has proposed a new pre-emphasis driver circuit which achieves wide noise margin by enlarging the signal voltage range during data transition. When data is transferred from a memory chip to a controller, the output boltage of the driver circuit reaches the final values through the intermediate voltage level. The proposed driver supplies more currents applicable to a packet-based memory system, because it needs no additional control signal and realizes very small area. The circuit has been designed in a 0.18 ${\mu}m$ CMOS process, and HSPICE simulation results have shown that the data rate of 1.32 Gbps be achieved. Due to its result, the proposed driver can achieved higher speed than conventional driver by 10%.