• Journal of the Institute of Electronics Engineers of Korea CI
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• v.38 no.6
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• pp.106-112
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• 2001

Unfortunately, the area without economical efficiency, especially the far distance sea, is much lower than that of a urban area-built-up area. It should be promoted the equivalent level to a urban area in the light of future-oriented universal service. Actually, Because propagation environment of mobile communication in the sea is greatly different from that for inland focused on built-up area, a propagation prediction model in the sea should be distinguished from inland-based one. Accordingly, the purpose of this study is to suggest the propagation prediction model for the sea service as a method to minimize unnecessary facilities investment and maintenance caused by additional or new building of a base station. If mobile phone service for far distance sea is provided by expanding limited communication zone of narrow band CDMA mobile communication whose spread band FA is 1.2288MHz. Suggested propagation prediction model includes five parameters to minimize facilities investment of a base station and maximize channel capacity: equivalent line of sight, chip delay by PN code, antenna altitude, power of base station and gain of antennas. Finally, suggested propagation prediction model is simulated and, the results are examined for its utility by comparing with loss of free space.

• Journal of IKEEE
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• v.21 no.4
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• pp.388-396
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• 2017

Since there are many variables such as various poses, illuminations and occlusions in a face detection problem, a high performance detection system is required. Although CNN is excellent in image classification, CNN operatioin requires high-performance hardware resources. But low cost low power environments are essential for small and mobile systems. So in this paper, the CPU-FPGA integrated system is designed based on 3-stage cascade CNN architecture using small size FPGA. Adaptive Region of Interest (ROI) is applied to reduce the number of CNN operations using face information of the previous frame. We use a Field Programmable Gate Array(FPGA) to accelerate the CNN computations. The accelerator reads multiple featuremap at once on the FPGA and performs a Multiply-Accumulate (MAC) operation in parallel for convolution operation. The system is implemented on Altera Cyclone V FPGA in which ARM Cortex A-9 and on-chip SRAM are embedded. The system runs at 30FPS with HD resolution input images. The CPU-FPGA integrated system showed 8.5 times of the power efficiency compared to systems using CPU only.

• Korean Journal of Optics and Photonics
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• v.6 no.3
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• pp.188-200
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• 1995

A design of unit magnification 2-mirror system with high resolution is presented. It is for soft X-ray(wavelength of 13 nm) projection imaging and suitable for preparation of high density semiconductor chip. In general, a holosymmetric system with unit magnification has the advantage that both coma and distortion are completely eliminated. In our holosymmetric 2-mirror system, spherical aberration is addtionally removed by using two identical paraboloidal mirror surfaces and field curvature aberration is also corrected by balancing Petzval sum and astigmatism which depends on the distance between two mirrors, so that the system is a aplanatic flat-field paraboloidal 2-mirror holosymmetric system. This 2-mirror system is small in size, and has a simple configuration with rotational symmetry about optical axis, and has also small central obscuration. Residual finite aberrations, spot diagrams, and diffraction-based MTF's are analyzed for the check of performances as soft X-ray lithography projection system. As a result, the image sizes for the resolutions of$0.25\mum$and $0.18\mum$are 4.0 mm, 2.5 mm respectively, and depths of focus for those are $2.5\mum$, $2.4\mum$respectively. This system should be useful in the fabrication of 256 Mega DRAM or 1 Giga DRAM. DRAM.

• Korean Journal of Environmental Agriculture
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• v.22 no.4
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• pp.261-265
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• 2003

In order to examine the difference in processing quality of potato tubers among localities, chemical properties of soils were analyzed and climatic conditions were investigated. Potatoes (Solanum tuberosum L.) were grown at seven localities of Korea during two years from 1994 to 1995. Soil samples and tubers were obtained from 2 to 3 commercial farms per locality with 10 days interval from 70 days before harvesting. As the result of that, higher correlation in processing quality was found with organic material content among soil conditions. On the climatic conditions, minimum temperature and sunshine hours during the period from 30 to 11 days before harvesting exhibited highly significant negative correlations with all quality parameters except reducing sugar content. Additionally, regression equations based on the observed level of these factors showed the relatively high coefficients of determination for dry matter content and chip color. To produce higher quality potatoes for processing, therefore, climatic conditions such as minimum temperature and sunshine hour and soil condition such as organic matter content have to be considered before the selection of areas or fields.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.430-439
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• 2004

This paper describes a design of 8192/2048-point FFT/IFFT processor (CFFT8k2k), which performs multi-carrier modulation/demodulation in OFDM-based DVB-T receiver. Since a large size FFT requires a large buffer memory, two design techniques are considered to achieve memory-efficient implementation of 8192-point FFT/IFFT. A hybrid structure, which is composed of radix-4 single-path delay feedback (R4SDF) and radix-4 single-path delay commutator (R4SDC), reduces its memory by 20% compared to R4SDC structure. In addition, a memory reduction of about 24% is achieved by a novel two-step convergent block floating-point scaling. As a result, it requires only 57% of memory used in conventional design, reducing chip area and power consumption. The CFFT8k2k core is designed in Verilog-HDL, and has about 102,000 Bates, RAM of 292k bits, and ROM of 39k bits. Using gate-level netlist with SDF which is synthesized using a $0.25-{\um}m$ CMOS library, timing simulation show that it can safely operate with 50-MHz clock at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. The functionality of the core is fully verified by FPGA implementation, and the average SQNR of 60-㏈ is achieved.

• Journal of Animal Environmental Science
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• v.16 no.3
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• pp.215-226
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• 2010

The pig slurry leachate was dark brown-colored solution that leaches out of woodchip trickling filter. The purpose of this research was to investigate the effect of pig slurry leachate and byproduct on growth characteristics of leaf lettuce in hydroponics culture. The effects of addition of fish meal, bone meal and crab shell for the growth of leaf lettuce were investigated. Leaf lettuce were grown in each of six combination treatment solutions; slurry leachate, slurry leachate + fish meal, slurry leachate+bone meal, slurry leachate + crab shell and chemical hydroponic solution for lettuce based on EC content. The chemical nutrient solution was the solution of National Horticulture Research Station for the growth of lettuce. The all of nutrient solution was adjusted 1.5 mS/cm in EC in hydroponics culture. 1. The pH level of leachate of trickling filter was increased and EC decreased gradually during treatment. Pig slurry leachate was low in suspended solids (SS), phosphorus (P), but rich in potassium (K). 2. The plot of slurry leachate (SL) was lowest in the growth characteristics of lettuce. The leaf length and width of lettuce treated with mixture plot of slurry leachate and fish meal (SL + FM) was higher compared with plot in slurry leachate. The chlorophyll reading was reduced in plot treated with slurry leachate, but that in plot of SL+FM was similar compared with control plot. 3. The fresh weight of lettuce showed lowest in the plot treated with slurry leachate. The addition of fish meal increased the yield of comparing plot of slurry leachate, but plots of bone meal and crab shell addition were not significantly difference. The fresh weight of leaf lettuce in plot of SL+FM was 87% as 400.0g compared with control. In conclusion, the mixture solution of pig slurry leachate and fish meal could be used as a nutrition solution of organic lettuce hydroponics.

• Korean Journal of Clinical Laboratory Science
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• v.51 no.4
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• pp.406-413
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• 2019

This study was undertaken to investigate the distribution of human papillomavirus (HPV) subtypes and cervical lesions in Busan. Furthermore, the cytological and histological findings of cervical lesions were compared to determine the usefulness of the currently released vaccines. HPV subtypes of 2,130 patients who visited Haeundae Paik Hospital between January 2013 and March 2016 were analyzed by the HPV 9G DNA chip. Liquid-based cytological examination was performed, and subtypes were classified according to the 2001 guidelines of The Bethesda System. Biopsy or hysterectomy specimens were subjected to hematoxylin and eosin staining for histological examinations. Of the total 2,130 cases, 1,254 (58.9%) were positive for HPV, and 876 (41.1%) were negative. Of these, 152 (7.1%), 97 (4.6%) and 80 (3.8%) were identified as HPV 16, 68 and 56, respectively. Of the 329 cases encompassing the above three HPV subtypes, histopathological analysis diagnosed 155 (47.1%) cases with CIN2 or higher grade. Notably, the occurrences of HPV subtypes 16, 68, 56, 58 and 51 were most frequently diagnosed in Busan. Further analysis revealed that administration of Gardasil^Ⓡ 9, the currently available vaccine in the market, exerts no protection against subtypes 68, 59 and 51. This study aims to provide an important reference for future HPV vaccination programs in Busan.

• Journal of Korean Tunnelling and Underground Space Association
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• v.21 no.1
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• pp.127-136
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• 2019

Tunnel construction by TBMs should be supported by the performance of a screw conveyor in order to obtain the optimum penetration rate, so studies related to the screw conveyor performance have been being conducted. Compared to the study on the performance of the screw conveyor for the soil, however, the research on the performance of the screw conveyor for the rock is insufficient. Considering the domestic tunnel sites with more rock layers than soil layers, simulation of discharge of 6 types of rock chips by the screw conveyor was conducted using DEM. Regardless of the shape and volume of the rock chips, the discharge rates of the rock chips by the parallel placed screw conveyor at a speed of 10 RPM in the same rock mass were about 20% (standard deviation: 1.3%) of the maximum volume of discharge rate by the screw conveyor. It is expected that this study can be used as a reference material for screw conveyor design and operation in TBM excavations in rock masses.

• Korean Journal of Remote Sensing
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• v.37 no.3
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• pp.431-447
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• 2021

Recently, the use of high-resolution satellites is increasing in many areas. In order to supply useful satellite images stably, it is necessary to establish automatic precision geometric correction technic. Geometric correction is the process that corrected geometric errors of satellite imagery based on the GCP (Ground Control Point), which is correspondence point between accurate ground coordinates and image coordinates. Therefore, in the automatic geometric correction process, it is the key to acquire high-quality GCPs automatically. In this paper, we proposed iterative precision geometry correction method. we constructed an image pyramid and repeatedly performed GCP chip matching, outlier detection, and precision sensor modeling in each layer of the image pyramid. Through this method, we were able to acquire high-quality GCPs automatically. we then improved the performance of geometric correction of high-resolution satellite images. To analyze the performance of the proposed method, we used KOMPSAT-3 and 3A Level 1R 8 scenes. As a result of the experiment, the proposed method showed the geometric correction accuracy of 1.5 pixels on average and a maximum of 2 pixels.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.7
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• pp.1071-1077
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• 2022

A security SoC that can be used to implement elliptic curve cryptography (ECC) based public-key infrastructures was designed. The security SoC has an architecture in which a hardware accelerator for the elliptic curve digital signature algorithm (ECDSA) is interfaced with the Cortex-A53 CPU using the AXI4-Lite bus. The ECDSA hardware accelerator, which consists of a high-performance ECC processor, a SHA3 hash core, a true random number generator (TRNG), a modular multiplier, BRAM, and control FSM, was designed to perform the high-performance computation of ECDSA signature generation and signature verification with minimal CPU control. The security SoC was implemented in the Zynq UltraScale+ MPSoC device to perform hardware-software co-verification, and it was evaluated that the ECDSA signature generation or signature verification can be achieved about 1,000 times per second at a clock frequency of 150 MHz. The ECDSA hardware accelerator was implemented using hardware resources of 74,630 LUTs, 23,356 flip-flops, 32kb BRAM, and 36 DSP blocks.