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http://dx.doi.org/10.7471/ikeee.2017.21.4.388

Cascade CNN with CPU-FPGA Architecture for Real-time Face Detection  

Nam, Kwang-Min (Dept. of Electronics Engineering, Kwangwoon University)
Jeong, Yong-Jin (Dept. of Electronics Engineering, Kwangwoon University)
Publication Information
Journal of IKEEE / v.21, no.4, 2017 , pp. 388-396 More about this Journal
Abstract
Since there are many variables such as various poses, illuminations and occlusions in a face detection problem, a high performance detection system is required. Although CNN is excellent in image classification, CNN operatioin requires high-performance hardware resources. But low cost low power environments are essential for small and mobile systems. So in this paper, the CPU-FPGA integrated system is designed based on 3-stage cascade CNN architecture using small size FPGA. Adaptive Region of Interest (ROI) is applied to reduce the number of CNN operations using face information of the previous frame. We use a Field Programmable Gate Array(FPGA) to accelerate the CNN computations. The accelerator reads multiple featuremap at once on the FPGA and performs a Multiply-Accumulate (MAC) operation in parallel for convolution operation. The system is implemented on Altera Cyclone V FPGA in which ARM Cortex A-9 and on-chip SRAM are embedded. The system runs at 30FPS with HD resolution input images. The CPU-FPGA integrated system showed 8.5 times of the power efficiency compared to systems using CPU only.
Keywords
Face Detection; Cascade Convolutional Neural Network (CNN); Hybrid FPGA; Acceleration; Energy Efficient;
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