• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.9-16
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• 2004

For a System-on-a-Chip(SoC) comprised of multiple IP cores, test control techniques have been developed to perform the internal and external test efficiently relying on the various design for testability techniques such as scan and BIST(Built-In Self-Test). However the test area overhead is too expensive to guarantee diverse test link configurations. In this paper, at first we introduce a new flag based Wrapped Core Linking Module(WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cores and P1500 wrapped cores. Then a simple test control technique, which can interconnect internal scan chains of different cores, is described with requiring least amount of area overhead compared with other state-of-art techniques. The design preserves compatibility with standards and scalability for hierarchical access.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.1004-1007
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• 2005

This paper presents a programmable RF BIST (Built-in Self-Test) circuit for low noise amplifiers. We have developed a new on-chip RF BIST circuit that measures RF parameters of low noise amplifier (LNA) using only DC measurements. The BIST circuit contains test amplifier with programmable capacitor banks and RF peak detectors. The test circuit utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance and gain using the mathematical equations. Our on-chip BIST can be self programmed for 1.8GHz, 2.4GHz and 5.25GHz LNA for GSM, Bluetooth and IEEE802.11g standards.

• Journal of the Korea Society of Computer and Information
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• v.21 no.1
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• pp.39-47
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• 2016

In this paper, we propose vehicle SoC fault diagnosis platform using FlexRay protocol in order to detect the faults of semiconductor control chip even after vehicle production. Before FlexRay protocol by sending NFI (Null Frame Indicator) bit among the header segment and a specific identifier in the payload segment of FlexRay frame, this technique can be distinguishable from normal mode and test mode. By using this technique, it is possible to detect the faults such as performance degradation of vehicle network system caused by the aging or several problems of vehicle semiconductor chip. Also high reliability and safety of vehicle can be maintained by using structural test for vehicle SoC fault detection.

• Proceedings of the KIEE Conference
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• 2004.05a
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• pp.153-155
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• 2004

In this paper, we design the memory tester chip playing an important role in the memory tester as central parts. Memory tester has the sixteen inner instructions to control the test sequence and the address and data signals to DUT. These instructions are saved in memory with each block such as sequencer and pattern generator. Sequencer controls the test sequence according to instructions saved in the memory. And Pattern generator generates the address and data signals according to instructions saved in the memory, too. We can use these chips for various functional test of memory.

• Proceedings of the KSME Conference
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• 2003.04a
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• pp.899-904
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• 2003

Microarrayer makes DNA chip and microarray that contain hundreds to thousands of immobilized DNA probes on surface of a microscope slide. This paper shows the development results for a printing type of microarrayer. It realizes a typical, low-cost and efficient microarrayer for generating low density microarray. The microarrayer is developed by using a robot of three-axes perpendicular type. It is composed of a computer-controlled three-axes robot and a pen tip assembly. The key component of the arrayer is the print-head containing the tips to immobilize cDNA, genomic DNA or similar biological material on glass surface. The robot is designed to automatically collect probes from two 96-well plates with up to 32 tips at the same time. To prove the performance of the developed microarrayer, the general water types of inks such as black, blue and red. The inks are distributed at proper positions of 96 well plates and the three color inks are immobilized on the slide glass under the operation procedure. As the result of the test, it can be shown that it has sufficient performance for the production of low integrated DNA chip consisted of 96 spots within 1 $cm^2$ area.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.16 no.5
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• pp.134-139
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• 2007

This paper presents a computer-based analysis on the thermal shock characteristics of Pb-free solder joints and UBM in flip chip assemblies. Among four types of popular UBM systems, TiW/Cu system with 95.5Sn-3.9Ag-0.6Cu solder joints was chosen for simulation. A simple 3D finite element model was first created only including silicon die, mixture between underfill and solder joints, and substrate. The displacements due to CTE mismatch between silicon die and substrate was then obtained through FE analysis. Finally, the obtained displacements were applied as mechanical loads to the whole 2D FE model and the characteristics of flip chip assemblies were analyzed. In addition, based on the hyperbolic sine law, the accumulated creep strain of Pb-free solder joints was calculated to predict the fatigue life of flip chip assemblies under thermal shock environments. The proposed method for fatigue life prediction will be evaluated through the cross check of the test results in the future work.

• Korean Journal of Materials Research
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• v.17 no.2
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• pp.91-95
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• 2007

Electromigration characteristics of Sn-3.5Ag flip chip solder bump were analyzed using flip chip packages which consisted of Si chip substrate and electroplated Cu under bump metallurgy. Electromigration test temperatures and current densities peformed were $140{\sim}175^{\circ}C\;and\;6{\sim}9{\times}10^4A/cm^2$ respectively. Mean time to failure of solder bump decreased as the temperature and current density increased. The activation energy and current density exponent were found to be 1.63 eV and 4.6, respectively. The activation energy and current density exponent have very high value because of high Joule heating. Evolution of Cu-Sn intermetallic compound was also investigated with respect to current density conditions.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.10
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• pp.840-846
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• 2000

In this work, small-size, high-performance solenoid-type RF chip inductors utilizing a low-loss Al$_2$O$_3$core material were investigated. The size of the chip inductors fabricated in this work were 15$\times$10$\times$0.7㎣, 2.1$\times$1.5$\times$10㎣, and 2.4$\times$2.0$\times$1.4㎣ and copper (Cu) wire with 40 ㎛ diameter was used as the coils. High frequency characteristics of the inductance, quality factor, and impedance of developed inductors were measured suing an RF Impedance/Material Analyzer (HP4291B with HP16193A test fixture). It was observed that the developed inductors with the number of turns of 7 have the inductance of 33 to 100nH and exhibit the self-resonant frequency (SRF) of .26 to 1.1 GHz. The SRF of inductors decreases with increasing the inductance and the inductors have the quality factor of 60 to 80 in the frequency range of 300 MHz to 1.1 GHz. In this study, small-size solenoid-type RF chip inductors with high inductance and high quality factor were fabricated successfully. It is suggested that the thin film-type inductor is necessary to fabricate the smaller size inductors at the expence of inductance and quality factor values.

• Geomechanics and Engineering
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• v.37 no.5
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• pp.443-452
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• 2024

The use of sand-tire chip mixtures in construction industry is a sustainable and environmentally friendly approach that addresses both waste tire disposal and soil improvement needs. However, the addition of tire chip particles to natural soils decreases maximum shear modulus (G_max), but increases compressibility, which can be potential drawbacks. This study examines the effect of overconsolidation stress history on the maximum shear modulus (G_max) of rigid-soft mixtures with varying size ratios (SR) and tire chip contents (TC) by measuring the wave velocity through a 1-D compression test during loading and unloading. The results demonstrate that the G_max of tested mixtures in the normally consolidated state increased with increasing SR and decreasing TC. However, the tested mixtures with a smaller SR exhibited a greater increase in G_max during unloading because of the active pore-filling behavior of the smaller rubber particles and the consequent increased connectivity between sand particles. The SR-dependent impact of the overconsolidation stress history on G_max was verified using the ratio between the swelling and compression indices. Most importantly, this study reveals that the excessive settlement and lower G_max of rigid-soft mixtures can be overcome by introducing an overconsolidated state in sand-tire chip mixtures with low TC.

• Nuclear Engineering and Technology
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• v.43 no.4
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• pp.391-398
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• 2011

The U metal chips generated in developing nuclear fuel and a gamma radioisotope shield have been stored under immersion of water in KAERI. When the water of the storing vessels vaporizes or drains due to unexpected leaking, the U metal chips are able to open to air. A new oxidation treatment process was raised for a long time safe storage with concepts of drying under vacuum, evaporating the containing water and organic material with elevating temperature, and oxidizing the uranium metal chips at an appropriate high temperature under conditions of controlling the feeding rate of oxygen gas. In order to optimize the oxidation process the uranium metal chips were completely dried at higher temperature than $300^{\circ}C$ and tested for oxidation at various temperatures, which are $300^{\circ}C$, $400^{\circ}C$, and $500^{\circ}C$. When the oxidation temperature was $400^{\circ}C$, the oxidized sample for 7 hours showed a temperature rise of $60^{\circ}C$ in the self-ignition test. But the oxidized sample for 14 hours revealed a slight temperature rise of $7^{\circ}C$ representing a stable behavior in the self-ignition test. When the temperature was $500^{\circ}C$, the shorter oxidation for 7 hours appeared to be enough because the self-ignition test represented no temperature rise. By using several chemical analyses such as carbon content determination, X-ray deflection (XRD), Infrared spectra (IR) and Thermal gravimetric analysis (TGA) on the oxidation treated samples, the results of self-ignition test of new oxidation treatment process for U metal chip were interpreted and supported.