• Title/Summary/Keyword: Chip flow

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Novel Bumping and Underfill Technologies for 3D IC Integration

  • Sung, Ki-Jun;Choi, Kwang-Seong;Bae, Hyun-Cheol;Kwon, Yong-Hwan;Eom, Yong-Sung
    • ETRI Journal
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    • v.34 no.5
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    • pp.706-712
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    • 2012
  • In previous work, novel maskless bumping and no-flow underfill technologies for three-dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low-volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no-flow underfill material named "fluxing underfill" is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two-tier stacked TSV chips are sucessfully stacked.

Hexagonal Material Flow Pattern for Next Generation Semiconductor Fabrication (차세대 반도체 펩을 위한 육각형 물류 구조의 설계)

  • Chung, Jae-Woo;Suh, Jung-Dae
    • Journal of Korean Institute of Industrial Engineers
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    • v.36 no.1
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    • pp.42-51
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    • 2010
  • The semiconductor industry is highly capital and technology intensive. Technology advancement on circuit design and process improvement requires chip makers continuously to invest a new fabrication facility that costs more than 3 billion US dollars. Especially major semiconductor companies recently started to discuss 450mm fabrication substituting existing 300mm fabrication of which facilities were initiated to build in 1998. If the plan is consolidated, the yield of 450mm facility would be more than doubled compared to existing 300mm facility. In steps of this important investment, facility layout has been acknowledged as one of the most important factors to be competitive in the market. This research proposes a new concept of semiconductor facility layout using hexagonal floor plan and its compatible material flow pattern. The main objective of this proposal is to improve the productivity of the unified layout that has been popularly used to build existing facilities. In this research, practical characteristics of the semiconductor fabrication are taken into account to develop a new layout alternative based on the analysis of Chung and Tanchoco (2009). The performance of the proposed layout alternative is analyzed using computer simulation and the results show that the new layout alternative outperforms the existing layout alternative, unified layout. However, a few questions on space efficiency to the new alternative were raised in communication with industry practitioners. These questions are left for a future study.

Cyclone Type Filter for Preventing Clogging of High Pressure Coolant Pump (고압 쿨런트 펌프의 막힘 방지를 위한 사이클론 타입 필터)

  • Kim, Jun-Hwan;Kang, Ji-Hun;Kang, Seong-Gi
    • Journal of the Korean Society of Manufacturing Technology Engineers
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    • v.24 no.6
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    • pp.599-604
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    • 2015
  • Currently, the coolant system in industrial sites is an efficient process to keep clean cutting oils. However, the damage to a pump occurs due to a chip and debris when inhaled into the pump, and thus problems such as the reduction of both efficiency and lifespan might arise. In this study, a new type of filter was developed in order to primarily prevent the damage from the pump impeller and make it unnecessary to have the replacement and cleaning at the same time. This study found the problem reducing the suction volumetric efficiency and cavitation when inhaled, and conducted a method to solve the problem compared to the result of fluid analysis according to two velocity conditions. As a result, this study achieved the effect of lowering the pressure and meeting the suction flow rate by connecting the four filters.

Flow Characteristics in a Microchannel Fabricated on a Silicon Wafer (실리콘 웨이퍼 상에 제작된 미소 유로에서의 유동특성)

  • Kim, Hyeong-U;Won, Chan-Sik;Jeong, Si-Yeong;Heo, Nam-Geon
    • Transactions of the Korean Society of Mechanical Engineers B
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    • v.25 no.12
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    • pp.1844-1852
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    • 2001
  • Recent developments in microfluidic devices based on microelectromechanical systems (MEMS) technique find many practical applications, which include electronic chip cooling devices, power MEMS devices, micro sensors, and bio-medical devices among others. For the design of such micro devices, flows characteristics inside a microchannel have to be clarified which exhibit somewhat different characteristics compared to conventional flows in a macrochannel. In the present study microchannels of various hydraulic diameters are fabricated on a silicon wafer to study the pressure drop characteristics. The effect of abrupt contraction and expansion is also studied. It is found from the results that the friction factor in a straight microchannel is about 15% higher than that in a conventional macrochannel, and the loss coefficients in abrupt expansion and contraction are about 10% higher than that obtained through conventional flow analysis.

Count-Min HyperLogLog : Cardinality Estimation Algorithm for Big Network Data (Count-Min HyperLogLog : 네트워크 빅데이터를 위한 카디널리티 추정 알고리즘)

  • Sinjung Kang;DaeHun Nyang
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.33 no.3
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    • pp.427-435
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    • 2023
  • Cardinality estimation is used in wide range of applications and a fundamental problem processing a large range of data. While the internet moves into the era of big data, the function addressing cardinality estimation use only on-chip cache memory. To use memory efficiently, there have been various methods proposed. However, because of the noises between estimator, which is data structure per flow, loss of accuracy occurs in these algorithms. In this paper, we focus on minimizing noises. We propose multiple data structure that each estimator has the number of estimated value as many as the number of structures and choose the minimum value, which is one with minimum noises, We discover that the proposed algorithm achieves better performance than the best existing work using the same tight memory, such as 1 bit per flow, through experiment.

Linear and Circular Interpolation for 2-Dimensional Contouring Control (2次元 輪곽制御 를 위한 直線 및 圓통補間)

  • 이봉진
    • Transactions of the Korean Society of Mechanical Engineers
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    • v.6 no.4
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    • pp.341-345
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    • 1982
  • The interpolator is usually built in hardware (logic circuitry), and the interpolator fabricated in a single LSI chip is recently made use of in most NC controllers, making the system more compact. However, the LSI interpolator not only has the technical difficulties but also requires high cost, in its fabrication. To solve these problems, we tried to find the method of interpolation by software, and succeeded in developing a program which, executed by INTEL's 8085 microprocessor, can distribute the input pulses of up to 4.0 [Kpps] for the linear interpolation and 3.0 [Kpps] for the circular interpolation. This paper presents the algorithm used to reduce the execution time and the flow chart of the interpolation program, and also shows the possibility of software interpolation. The interpolation program designed in assembly language is presented in the appendix.

Pre-layout Clock Analysis with Static Timing Analysis Algorithm to Optimize Clock Tree Synthesis (Static Timing Analysis (STA) 기법을 이용한 Clock Tree Synthesis (CTS) 최적화에 관한 연구)

  • Park, Joo-Hyun;Ryu, Seong-Min;Jang, Myung-Soo;Choi, Sea-Hawon;Choi, Kyu-Myung;Cho, Jun-Dong;Kong, Jeong-Taek
    • Proceedings of the KIEE Conference
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    • 2004.11c
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    • pp.391-393
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    • 2004
  • For performance and stability of a synchronized system, we need an efficient Clock Tree Synthesis(CTS) methodology to design clock distribution networks. In a system-on-a-chip(SOC) design environment, CTS effectively distributes clock signals from clock sources to synchronized points on layout design. In this paper, we suggest the pre-layout analysis of the clock network including gated clock, multiple clock, and test mode CTS optimization. This analysis can help to avoid design failure with potential CTS problems from logic designers and supply layout constraints so as to get an optimal clock distribution network. Our new design flow including pre-layout CTS analysis and structural violation checking also contributes to reduce design time significantly.

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The estimation of tool wear and fracture mechanism using sensor fusion in micro-machining (미세형상가공시 센서융합을 이용한 공구 마멸 및 파손 메커니즘 검출)

  • 임정숙;왕덕현;김원일;이윤경
    • Proceedings of the Korean Society of Machine Tool Engineers Conference
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    • 2002.04a
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    • pp.245-250
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    • 2002
  • A successful on-line monitoring system for conventional machining operations has the potential to reduce cost, guarantee consistency of product quality, improve productivity and provide a safer environment for the operator. In fee-shape machining, typical signs of tool problems such as vibration, noise, chip flow characteristics and visual signs are almost unnoticeable without the use of special equipment. These characteristics increase the importance of automatic monitoring in fine-shape machining; however, sensing and interpretation of signals are more complex. In addition, the shafts of the micro-tools break before the typical extensive cutting edge of the tool gets damaged. In this study, the existence of a relationship between the characteristics of the cutting force and tool usage was investigated, and tool breakage detection algorithm was developed and the fellowing results are obtained. In data analysis, didn't use a relative error compare which mainly used in established experiment and investigated tool breakage detection algorithm in time domain which can detect AE and cutting force signals more effective and accurate.

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3차원 절삭가공에서의 2자유도 채터안정성 해석

  • 김병룡;강명창;김정석
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2001.10a
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    • pp.31-35
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    • 2001
  • Three dimensional dynamic cutting can be postulated as an equivalent orthogonal dynamic cutting through the plane containing both the cutting vector and the chip flow velocity vector in cutting process. An analytical expression of dynamic cutting force is obtained from the cutting parameters determined by the static three dimensional cutting experiments. Particular attention is paid to the energy supplied to the vibration of the tool behind the vertical vibration and the direction. The phase lag of the horizontal vibration of the tool behind the vertical vibration and the direction angel of the fluctuating cutting force must be regarded in point of stability limits. Chatter vibration can effectively be suppressed by enlarging the dynamic rigidity of the cutting system in the vertical cutting force direction. A good agreement is found between the stability limits predicted by theory and the critical width of cut determined by experiments.

A Study About Biochip Combined with Micro Mixer and Reactor for DNA Ligation (마이크로 혼합기와 반응기로 구성된 DNA 결찰용 바이오칩에 관한 연구)

  • Kang, Do-Hyoung;Ahn, Yoo-Min;Hwang, Seung-Yong
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.32 no.8
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    • pp.624-632
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    • 2008
  • In this research, we developed new PDMS-glass based microbiochip consisted of the micromixer and microreactor for DNA ligation. The micromixer was composed of a straight channel integrated with nozzles and pillars, and the microreactor was composed of a serpentine channel. We coated the PDMS chip surface with the 0.25wt.% PVP solution to prevent the bubble generation which was caused by the hydrophobicity of the PDMS. The new micomixer was passive type and the mixing was enhanced by a convective diffusion using the nozzle and pillar. The 10.33mm long micromixer showed the good mixing efficiency of 87.7% at 500 l/min flow rate. We could perform the DNA ligation successfully in the microbiochip, and the ligation time was shortened from 4 hours in conventional laboratory method to 5 min in the microbiochip.