• Title/Summary/Keyword: Chip fabrication

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A Miniaturized 2.5 GHz 8 W GaN HEMT Power Amplifier Module Using Selectively Anodized Aluminum Oxide Substrate (선택적 산화 알루미늄 기판을 이용한 소형 2.5 GHz 8 W GaN HEMT 전력 증폭기 모듈)

  • Jeong, Hae-Chang;Oh, Hyun-Seok;Yeom, Kyung-Whan
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.12
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    • pp.1069-1077
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    • 2011
  • In this paper, a design and fabrication of a miniaturized 2.5 GHz 8 W power amplifier using selectively anodized aluminum oxide(SAAO) substrate are presented. The process of SAAO substrate is recently proposed and patented by Wavenics Inc. which uses aluminum as wafer. The selected active device is a commercially available GaN HEMT chip of TriQuint company, which is recently released. The optimum impedances for power amplifier design were extracted using the custom tuning jig composed of tunable passive components. The class-F power amplifier are designed based on EM co-simulation of impedance matching circuit. The matching circuit is realized in SAAO substrate. For integration and matching in the small package module, spiral inductors and single layer capacitors are used. The fabricated power amplifier with $4.4{\times}4.4\;mm^2$ shows the efficiency above 40 % and harmonic suppression above 30 dBc for the second(2nd) and the third(3rd) harmonic at the output power of 8 W.

Design of a Broadband Printing RFID Tag Antenna with Low Performance Degradation Due to Nearby Dielectric Material (근접 유전체에 의한 성능 열화가 적은 광대역 프린팅 태그 안테나 설계)

  • Ji, Sung-Hwan;Han, Won-Keun;Park, Ik-Mo;Choo, Ho-Sung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.20 no.8
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    • pp.694-700
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    • 2009
  • In this paper, we propose a RFID tag antenna with low performance degradation due to nearby dielectric materials. The proposed antenna is designed to be appropriate for ink printing fabrication. The antenna is designed to operate in UHF band of $860{\sim}960$ MHz. The antenna uses a T-matching network in the middle of the main body and two parasitic patches in vicinity for complex conjugate matching with a commercial tag chip. In addition, the two parasitic patches induce currents at different dielectric constants of nearby dielectric materials. This can minimize the performance degradation due to nearby dielectric materials. The measured results show the half power matching bandwidth from 844 MHT to 1,268 MHz. It exhibits the reading distance of about 3.5 m in free space when the tag antenna is used with the commercial reader antenna (transmitting power of 20 dBm and the reader antenna gain of 6 dBi). When the tag is attached on dielectric materials of wood and FR4, the resulting reading distances are 2.61 m and 2.51 m, respectively.

Adiabatic Optical-fiber Tapers for Efficient Light Coupling between Silicon Waveguides and Optical Fibers (실리콘 도파로와 광섬유 사이의 효율적인 광 결합을 위한 아디아바틱 광섬유 테이퍼)

  • Son, Gyeongho;Choi, Jiwon;Jeong, Youngjae;Yu, Kyoungsik
    • Korean Journal of Optics and Photonics
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    • v.31 no.5
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    • pp.213-217
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    • 2020
  • In this study we report a wet-etching-based fabrication method for adiabatic optical-fiber tapers (OFTs), and describe their adiabaticity and HE11 mode evolution at a wavelength of 1550 nm. The profile of the fabricated system satisfies the adiabaticity properties well, and the far-field pattern from the etched OFT shows that the fundamental HE11 mode is maintained without a higher-order mode coupling throughout the tapers. In addition, the measured far-field pattern agrees well with the simulated result. The proposed adiabatic OFTs can be applied to a number of photonic applications, especially fiber-chip packages. Based on the fabricated adiabatic OFT structures, the optical transmission to the inversely tapered silicon waveguide shows large spatial-dimensional tolerances for 1 dB excess loss of ~60 ㎛ (silicon waveguide angle of 1°) and insertion loss of less than 0.4 dB (silicon waveguide angle of 4°), from the numerical simulation. The proposed adiabatic coupler shows the ultrabroadband coupling efficiency over the O- and C-bands.

Fabrication of Porous Reticular Metal by Electrodeposition of Fe/Ni Alloy for Heat Dissipation Materials (Fe/Ni 합금전착에 의한 다공성 그물군조 방열재료의 제조 연구)

  • Lee, Hwa-Young;Lee, Kwan-Hyi;Jeung, Won-Young
    • Journal of the Korean Electrochemical Society
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    • v.5 no.3
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    • pp.125-130
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    • 2002
  • An attempt was made for the application of porous reticular metal to a heat dissipation material in semiconductor process. For this aim, the electrodeposition of Fe/Ni alloy on the porous reticular Cu has been performed to minimize the thermal expansion mismatch between Cu skeleton and electronic chip. Preliminary tests for the electrodeposition of Fe/Ni alloy layer were conducted by using standard Hull Cell to examine the effect of current density on the composition of alloy layer. It seemed that mass transfer affected significantly the composition of Fe/Ni layer due to anomalous codeposition in the electrodeposition of Fe/Ni alloy. A paddle type stirring bath, which was employed to control the mass transfer of electrolyte in the work, was found to allow the electrodeposition Fe/Ni with a precise composition. result showed that the thermal expansion of Fe/Ni alloy layer was much lower than that of pure copper. From the tests of heat dissipation by using the apparatus designed in the work the heat dissipation material fabricated in the work showed the excellent heat dissipation capacity, namely, more than two times as compared to that of pure copper plate.

Design and fabrication of the MMIC frequency doubler for 29 GHz local oscillator application (29GHz 국부 발진 신호용 MMIC 주파수 체배기의 설계 및 제작)

  • Kim, Jin-Sung;Lee, Seong-Dae;Lee, Bok-Hyoung;Kim, Sung-Chan;Sul, Woo-Suk;Lim, Byeong-Ok;Kim, Sam-Dong;Park, Hyun-Chang;Park, Hyung-Moo;Rhee, Jin-Koo
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.38 no.11
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    • pp.63-70
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    • 2001
  • We demonstrate the MMIC (monolithic microwave integrated circuit) frequency doublers generating stable and low-cost 29 GHz local oscillator signals from 14.5 GHz input signals. These devices were designed and fabricated by using the M MIC integration process of $0.1\;{\mu}m$ gate-length PHEMTs (pseudomorphic high electron mobility transistors) and passive components. The measurements showed S11 or -9.2 dB at 145 GHz, S22 of -18.6 dG at 29 GHz and a minimum conversion loss of 18.2 dB at 14.5 GHz with an input power or 6 dBm. Fundamental signal of 14.5 GHz were suppressed below 15.2 dBe compared to the second harmonic signal at the output port, and the isolation characteristics of fundamental signal between the input and the output port were maintained above :i0 dB in the frequency range 10.5 GHz to 18.5 GHz. The chip size of the fabricated MMIC frequency doubler is $1.5{\times}2.2\;mm^2$.

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Fabrication of passive-aligned optical sub-assembly for optical transceiver using silicon optical bench (실리콘 광학벤치를 사용한 수동정렬형 광송수신기용 광부모듈의 제작)

  • Lee, Sang-Hwan;Joo, Gwan-Chong;Hwang, nam;moon, Jong-Tae;Song, Min-Kyu;Pyun, Kwang-Eui;Lee, Yong-Hyun
    • Korean Journal of Optics and Photonics
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    • v.8 no.6
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    • pp.510-515
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    • 1997
  • Packaging takes an extremely important element of optical module cost due primarily to the added complication of alignment between semiconductor devices and optical fiber, and many efforts have been devoted on reducing the cost by eliminating the complicated optical alignment procedures in passive manner. In this study, we fabricated silicon optical benches on which the optical alignments are accomplished passively. To improve the positioning accuracy of a flip-chip bonded LD, we adopted fiducial marks and solder dams which are self-aligned with V-groove etch patterns, and a stand-off to control the height and to improve the heat dissipation of LD. Optical sub-assemblies exhibited an average efficiency of -11.75$\pm$1.75 dB(1$\sigma$) from the LD-to-single mode fiber coupling and an average sensitivity of -35.0$\pm$1.5 dBm from the fiber and photodetector coupling.

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Design of a radiation-tolerant I-gate n-MOSFET structure and analysis of its characteristic (I 형 게이트 내방사선 n-MOSFET 구조 설계 및 특성분석)

  • Lee, Min-woong;Cho, Seong-ik;Lee, Nam-ho;Jeong, Sang-hun;Kim, Sung-mi
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.10
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    • pp.1927-1934
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    • 2016
  • In this paper, we proposed a I-gate n-MOSFET (n-type Metal Oxide Semiconductors Field Effect Transistor) structure in order to mitigate a radiation-induced leakage current path in an isolation oxide interface of a silicon-based standard n-MOSFET. The proposed I-gate n-MOSFET structure was designed by using a layout modification technology in the standard 0.18um CMOS (Complementary Metal Oxide Semiconductor) process, this structure supplements the structural drawbacks of conventional radiation-tolerant electronic device using layout modification technology such as an ELT (Enclosed Layout Transistor) and a DGA (Dummy Gate-Assisted) n-MOSFET. Thus, in comparison with the conventional structures, it can ensure expandability of a circuit design in a semiconductor-chip fabrication. Also for verification of a radiation-tolerant characteristic, we carried out M&S (Modeling and Simulation) using TCAD 3D (Technology Computer Aided Design 3-dimension) tool. As a results, we had confirmed the radiation-tolerant characteristic of the I-gate n-MOSFET structure.

Paraboloidal 2-mirror Holosymmetric System with Unit Maginification for Soft X-ray Projection Lithography (연X-선 투사 리소그라피를 위한 등배율 포물면 2-반사경 Holosymmetric System)

  • 조영민;이상수
    • Korean Journal of Optics and Photonics
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    • v.6 no.3
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    • pp.188-200
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    • 1995
  • A design of unit magnification 2-mirror system with high resolution is presented. It is for soft X-ray(wavelength of 13 nm) projection imaging and suitable for preparation of high density semiconductor chip. In general, a holosymmetric system with unit magnification has the advantage that both coma and distortion are completely eliminated. In our holosymmetric 2-mirror system, spherical aberration is addtionally removed by using two identical paraboloidal mirror surfaces and field curvature aberration is also corrected by balancing Petzval sum and astigmatism which depends on the distance between two mirrors, so that the system is a aplanatic flat-field paraboloidal 2-mirror holosymmetric system. This 2-mirror system is small in size, and has a simple configuration with rotational symmetry about optical axis, and has also small central obscuration. Residual finite aberrations, spot diagrams, and diffraction-based MTF's are analyzed for the check of performances as soft X-ray lithography projection system. As a result, the image sizes for the resolutions of$0.25\mum$and $0.18\mum$are 4.0 mm, 2.5 mm respectively, and depths of focus for those are $2.5\mum$, $2.4\mum$respectively. This system should be useful in the fabrication of 256 Mega DRAM or 1 Giga DRAM. DRAM.

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Implant Isolation Characteristics for 1.25 Gbps Monolithic Integrated Bi-Directional Optoelectronic SoC (1.25 Gbps 단일집적 양방향 광전 SoC를 위한 임플란트 절연 특성 분석)

  • Kim, Sung-Il;Kang, Kwang-Yong;Lee, Hai-Young
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.8
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    • pp.52-59
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    • 2007
  • In this paper, we analyzed and measured implant isolation characteristics for a 1.25 Gbps monolithic integrated hi-directional (M-BiDi) optoelectronic system-on-a-chip, which is a key component to constitute gigabit passive optical networks (PONs) for a fiber-to-the-home (FTTH). Also, we derived an equivalent circuit of the implant structure under various DC bias conditions. The 1.25 Gbps M-BiDi transmit-receive SoC consists of a laser diode with a monitor photodiode as a transmitter and a digital photodiode as a digital data receiver on the same InP wafer According to IEEE 802.3ah and ITU-T G.983.3 standards, a receiver sensitivity of the digital receiver has to satisfy under -24 dBm @ BER=10-12. Therefore, the electrical crosstalk levels have to maintain less than -86 dB from DC to 3 GHz. From analysed and measured results of the implant structure, the M-BiDi SoC with the implant area of 20 mm width and more than 200 mm distance between the laser diode and monitor photodiode, and between the monitor photodiode and digital photodiode, satisfies the electrical crosstalk level. These implant characteristics can be used for the design and fabrication of an optoelectronic SoC design, and expended to a mixed-mode SoC field.