• Molecules and Cells
• /
• v.45 no.2
• /
• pp.76-83
• /
• 2022

Neurons-on-a-Chip technology has been developed to provide diverse in vitro neuro-tools to study neuritogenesis, synaptogensis, axon guidance, and network dynamics. The two core enabling technologies are soft-lithography and microelectrode array technology. Soft lithography technology made it possible to fabricate microstamps and microfluidic channel devices with a simple replica molding method in a biological laboratory and innovatively reduced the turn-around time from assay design to chip fabrication, facilitating various experimental designs. To control nerve cell behaviors at the single cell level via chemical cues, surface biofunctionalization methods and micropatterning techniques were developed. Microelectrode chip technology, which provides a functional readout by measuring the electrophysiological signals from individual neurons, has become a popular platform to investigate neural information processing in networks. Due to these key advances, it is possible to study the relationship between the network structure and functions, and they have opened a new era of neurobiology and will become standard tools in the near future.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
• /
• 2000.11a
• /
• pp.219-224
• /
• 2000

This paper presents a ripple reduction of BLDC motor using TMS320F240. A fault of permanent magnet(PM) BLDC motor possible to miniaturization and high-output is to be difficult to reduce speed-ripple at low speed region. An existing solution is to be use of PWM waveform by PI control with computing control angle of 60$^{\circ}$. The new family of DSP controllers provides a single chip solution by integrating on-chip not only a high computational power but also, all the peripherals necessary for electric motor control. This paper gives an advanced solution of the SVPWM technique for the purpose of reducing control angel rather than 60$^{\circ}$. This technique gives an excellent speed ripple characteristic.

• 제어로봇시스템학회:학술대회논문집
• /
• 2001.10a
• /
• pp.86.5-86
• /
• 2001

This work describes a design and implementation of the level & flow rate control system by using a single-chip microcontroller. The proposed model system is designed based on the use of the single-chip microcontroller 8031 with the EPROM emulator for programming the computer software. The microcontroller reaches the input level and flow signals from the level sensor and the turbine flowmeter, respectively, via the signal conditioning circuits and A/D converters in order to calculate the control signal. Moreover, the status of the process variable can easily be set up and controlled by program monitoring through the emulator, and can be graphically displayed on the computer screen. Experiment results were carried out which can be ...

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.15 no.8
• /
• pp.5195-5200
• /
• 2014

White LEDs are expected to be applied widely as a lighting system. To make white LED chips, one requires a mixture with silicon and a phosphor coating on a LED blue chip. The process of preparing a mixture with silicon using phosphor involves the use of discarded phosphor in the chip process. Reducing the costs of chip production depends on many factors, such as the mixture errors, exposure over time of silicon, and changes in the characteristics of blue chip. This paper reports the characteristics of a white LED chip manufactured through a reproduction process of derelict phosphor. This method was applicable to a real LED flashlight. A derelict phosphor chip showed similar results to a normal white chip for the degradation of cd 3.2[Cd] and 3.6[Cd], color temperature, 57[K] and 58[K], and maximum white wavelength 444.3[nm] and 449.8[nm]. These results are expected to make ea great contribution to cost reduction.

• KSBB Journal
• /
• v.20 no.3
• /
• pp.197-204
• /
• 2005

Lab-on-a-chip is a miniaturized analytical device in which all of the procedures for the analysis of molecules are carried out, such as pretreatment, reaction, separation, detection, etc. Lab-on-a-chip has increasing concern as a device not only for rapid detection of molecules but also for high throughput screening and point of care, because conventional laborious and time consuming analytical procedures can be substituted. Thus, a lot of microfabrication and analytical techniques for lab-on-a-chip have been developed with microstructures smaller than a few hundreds of micrometers. Separation of the molecules is one of the most important components of lab-on-a-chip, because effective separation method can simplify the design and can provide better sensitivity. The electrokinetic separation based on capillary electrophoresis is most widely employed technique in lab-on-a-chip for the control of fluids and the separation of molecules. In this article, bioseparation techniques and its applications realized in lab-on-a-chip are reviewed.

• Transactions of the Korean Society for Noise and Vibration Engineering
• /
• v.21 no.8
• /
• pp.768-773
• /
• 2011

This work presents an experimental investigation on vibration control of the active hybrid mount system for naval ships. To reduce unwanted vibrations, this paper proposes an active mount which consists of rubber element, piezostack actuator and inertial mass. The rubber element supports a mass. The piezostack actuator generates a proper control force and supply it to the mount system. To avoid being broken piezostack actuator, an actuator of the proposed mount is devised as an inertial type, in which a piezostack actuator is positioned between inertial mass and rubber element. Vibration control performances of the active mount system are evaluated via experiment. To attenuate the unwanted vibrations transferred from upper mass, the feedforward control is designed. In order to implement a control experiment, the active mount system supported by four active mounts is constructed. For realization of the controller, one-chip board is manufactured and utilized. Subsequently, vibration control performances of the proposed active mount system are experimentally evaluated in frequency domains.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.17 no.2
• /
• pp.353-368
• /
• 2023

The four wing unmanned aerial vehicle owns the characteristics of small size, light weight, convenient operation and well stability. But it is easily disturbed by external environmental factors during flight with these disadvantages of short endurance and poor attitude solving ability. For solving these problems, a microprocessor based on STM32 chip is designed and the overall development is completed by the resources such as built-in timer and multi-function mode general-purpose input/output provided by the master micro controller unit, together with radio receiver, attitude meter, barometer, electronic speed control and other devices. The unmanned aerial vehicle can be remotely controlled and send radio waves to its corresponding receiver, control the analog level change of its corresponding channel pins. The master control chip can analyze and process the data to send multiple sets pulse signals of pulse width modulation to each electronic speed control. Then the electronic speed control will transform different pulse signals into different sizes of current value to drive the motor located in each direction of the frame to generate different rotational speed and generate lift force. To control the body of the unmanned aerial vehicle, so as to achieve the operator's requirements for attitude control, the PID controller based on Kalman filter is used to achieve quick response time and control accuracy. Test results show that the design is feasible.

• Proceedings of the Korean Institute of Intelligent Systems Conference
• /
• 1993.06a
• /
• pp.975-976
• /
• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• Journal of the Microelectronics and Packaging Society
• /
• v.25 no.1
• /
• pp.41-45
• /
• 2018

As the size of semiconductor chip shrinks, the electronic industry has been paying close attention to fan-out wafer level packaging (FO-WLP) as an emerging solution to accommodate high input and output density. FO-WLP also has several advantages, such as thin thickness and good thermal resistance, compared to conventional packaging technologies. However, one major challenge in current FO-WLP manufacturing process is to control wafer warpage, caused by the difference of coefficient of thermal expansion and Young's modulus among the materials. Wafer warpage induces misalignment of chips and interconnects, which eventually reduces product quality and reliability in high volume manufacturing. In order to control wafer warpage, it is necessary to understand the effect of material properties and design parameters, such as chip size, chip to mold ratio, and carrier thickness, during packaging processes. This paper focuses on the effects of thickness of chip and molding compound on 12" wafer warpage after PMC of EMC using finite element analysis. As a result, the largest warpage was observed at specific thickness ratio of chip and EMC.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.30 no.6
• /
• pp.518-521
• /
• 2019

In this paper, an active antenna module operating in the 60 GHz band is designed and fabricated by combining a commercial transmitter chip and patch array antenna. The designed module is composed of an antenna PCB and a PCB with a transmitter chip. The frequency-control and bias-control signals are applied to the transmitter chip, using an Arduino kit. A baseband I/Q signal is also applied to the chip. A ring hybrid balun converts the output of the transmitter module to a single output, which is the output of the transmitter chip that outputs a differential output. The output is delivered to the $2{\times}4$ microstrip patch array antenna PCB as a micro-computer connector. The radiation pattern of the millimeter-wave signal of the final output is compared with the simulation results. The measured radiation patterns of the fabricated active antenna module confirm that the positions of the 3 dB beam width and null point agree well with the simulation results.