• Journal of Information Processing Systems
• /
• v.2 no.3 s.4
• /
• pp.189-193
• /
• 2006

In this study we propose an automatic reading system for diagnostic DNA chips. We define a general specification for an automatic reading system and propose a possible implementation method. The proposed system performs the whole reading process automatically without any user intervention, covering image acquisition, image analysis, and report generation. We applied the system for the automatic report generation of a commercialized DNA chip for cervical cancer detection. The fluorescence image of the hybridization result was acquired with a $GenePix^{TM}$ scanner using its library running in HTML pages. The processing of the acquired image and the report generation were executed by a component object module programmed with Microsoft Visual C++ 6.0. To generate the report document, we made an HWP 2002 document template with marker strings that were supposed to be searched and replaced with the corresponding information such as patient information and diagnosis results. The proposed system generates the report document by reading the template and changing the marker strings with the resultant contents. The system is expected to facilitate the usage of a diagnostic DNA chip for mass screening by the automation of a conventional manual reading process, shortening its processing time, and quantifying the reading criteria.

• Journal of Sensor Science and Technology
• /
• v.18 no.3
• /
• pp.190-196
• /
• 2009

In a conventional camera system, a target tracking system consists of a camera part and a image processing part. However, in the field of the real time image processing, the vision chip for edge detection which was made by imitating the algorithm of humanis retina is superior to the conventional digital image processing systems because the human retina uses the parallel information processing method. In this paper, we present a high speed target tracking system using the function of the CMOS vision chip for edge detection.

• 제어로봇시스템학회:학술대회논문집
• /
• 2005.06a
• /
• pp.838-841
• /
• 2005

DNA Chip is able to show DNA-Data that includes diseases of sample to User by using complementary characters of DNA. So this paper studied Neural Network algorithm for Image data processing of DNA-chip. DNA chip outputs image data of colors and intensities of lights when some sample DNA is putted on DNA-chip, and we can classify pattern of these image data on user pc environment through artificial neural network and some of image processing algorithms. Ultimate aim is developing of pattern classifying algorithm, simulating this algorithm and so getting information of one's diseases through applying this algorithm. Namely, this paper study artificial neural network algorithm for classifying pattern of image data that is obtained from DNA-chip. And, by using histogram, gradient edge, ANN and learning algorithm, we can analyze and classifying pattern of this DNA-chip image data. so we are able to monitor, and simulating this algorithm.

• Journal of the Korean Society of Manufacturing Process Engineers
• /
• v.11 no.4
• /
• pp.147-153
• /
• 2012

The demands of the large scale machine tools, for instance, such as planomiller, turning machine, boring machine, NC machine, have been gradually increased in recent years. As the performances of machine tools and/or cutting tools are advanced, it is possible to perform high-speed and high-precision cutting works. The effective treatment of wet chip, which is discharged from cutting works, becomes very important problems. Therefore, this study is forced on the design of large scale machine tools using CATIA V5R18 and analysis of cutter, which is considered as essential equipment in large scale machine tools, using MSC.Nastran & MSC.Patran. Especially, the relations between tolerated load of cutter, driving horse power and rpm of driving shaft in chip processing system are investigated through analysis. As the results, the reliability of design could be improved by evaluating simulated numerical values, it showed that tolerated loads of supported part and edged part of cutter are 87,000N and 14,450N, respectively.

• Journal of the Institute of Convergence Signal Processing
• /
• v.10 no.2
• /
• pp.120-126
• /
• 2009

There are many different types of surface defects on semiconductor Integrated Chips (IC's) caused by various factors during manufacturing process, such as cracks, foreign materials, chip-outs, chips, and voids. These defects must be detected and classified by an inspection system for productivity improvement and effective process control. Among defects, in particular, foreign materials and chips are the most difficult ones to classify accurately. A vision system composed of a carefully designed optical system and a processing algorithm is proposed to detect and classify the defects on QFN(Quad Flat No-leads) packages. The processing algorithm uses features derived from the defect's position and brightness value in the Maximum Likelihood classifier and the optical system is designed to effectively extract the features used in the classifier. In experiments we confirm that this method gives more effective result in classifying foreign materials and chips.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.58 no.7
• /
• pp.1418-1423
• /
• 2009

This paper describes the design and implementation of a System-on-a-Chip (SoC) for image processing applications to use in wearable/mobile products. The target Soc consists of LEON 2 core, AMBA/APB bus-systems and custom-designed controllers. A new FPGA-based prototyping platform is implemented and used for design and verification of the target SoC. To ensure that the implemented SoC satisfies the required performances, an image processing application is performed.

• Proceedings of the KSR Conference
• /
• 2008.06a
• /
• pp.572-578
• /
• 2008

As the railway transportation is getting faster and its operation speed has increased rapidly, its signal control has been complicated. For real time signal processing it is very important to prohibit any critical error from causing the system to malfunction. Therefore, handling complicated signals effectively while maintaining fault-tolerance capability is highly expected in modern railway transportation industry. In this paper, we suggest an SoC (Sytem-on-Chip) design method to integrate these complicated signal controlling mechanism with fault tolerant capability in a single chip. We propose an SoC solution which contains a high performance 32-bit embedded processor, digital filters and a PWM unit inside a single chip to implement ATO's, ATC's, ATP's and ATS's digital signal-processing units. We achieve an enhanced reliability against the calculation error by adding fault tolerance features to ensure the stability of each module.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.10
• /
• pp.161-172
• /
• 1994

This paper describes the design of a neurochip with on-chip learning capability in hardware with multiple processing elements. A digital architecture is adopted because its flexiblity and accuracy is advantageous for simulating the various application systems. The proposed chip consists of several processing elements to fit the large computation of neural networks, and has on-chip learning capability based on error back-propagation algorithm. It also minimizes the number of blobal control signals for processing elements. The modularity of the system makes it possible to buil various kinds of boards to match the expected range of applications.

• Journal of Sensor Science and Technology
• /
• v.13 no.3
• /
• pp.188-194
• /
• 2004

With a remarkable advance in CMOS (complimentary metal-oxide-semiconductor) process technology, a variety of vision sensors with signal processing circuits for complicated functions are actively being developed. Especially, as the principles of signal processing in human retina have been revealed, a series of vision chips imitating human retina have been reported. Human retina is able to detect the edge and motion of an object effectively. The edge detection among the several functions of the retina is accomplished by the cells called photoreceptor, horizontal cell and bipolar cell. We designed a CMOS vision chip by modeling cells of the retina as hardwares involved in edge and motion detection. The designed vision chip was fabricated using $0.6{\mu}m$ CMOS process and the characteristics were measured. Having reliable output characteristics, this chip can be used at the input stage for many applications, like targe tracking system, fingerprint recognition system, human-friendly robot system and etc.

• IEIE Transactions on Smart Processing and Computing
• /
• v.4 no.2
• /
• pp.65-70
• /
• 2015

In this paper, we describe the world's first real-time ray-tracing chip architecture. Ray-tracing technology generates high-quality 3D graphics images better than current rasterization technology by providing four essential light effects: shadow, reflection, refraction and transmission. The real-time ray-tracing chip named RayChip includes a real-time ray-tracing graphics processing unit and an accelerating tree-building unit. An ARM Ltd. central processing unit (CPU) and other peripherals are also included to support all processes of 3D graphics applications. Using the accelerating tree-building unit named RayTree to minimize the CPU load, the chip uses a low-end CPU and decreases both silicon area and power consumption. The evaluation results with RayChip show appropriate performance to support real-time ray tracing in high-definition (HD) resolution, while the rendered images are scaled to full HD resolution. The chip also integrates the Linux operating system and the familiar OpenGL for Embedded Systems application programming interface for easy application development.