Design of a Neurochip's Core with on-chip Learning Capability on Hardware with Minimal Global Control

On-chip 학습기능을 구현한 최소 광역 제어 신경회로망 칩의 코어 설계

This paper describes the design of a neurochip with on-chip learning capability in hardware with multiple processing elements. A digital architecture is adopted because its flexiblity and accuracy is advantageous for simulating the various application systems. The proposed chip consists of several processing elements to fit the large computation of neural networks, and has on-chip learning capability based on error back-propagation algorithm. It also minimizes the number of blobal control signals for processing elements. The modularity of the system makes it possible to buil various kinds of boards to match the expected range of applications.