• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2002년도 추계학술대회 논문집
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• pp.270-273
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• 2002

This paper presents an effective cutting force model that enable us to predict the instantaneous cutting force in milling process from a knowledge of the work material properties and cutting conditions. The development of the model is based on the orthogonal machining theory with the effective rake angle which is defined in the plane containing the cutting velocity and chip flow vectors. Face milling tests are performed at different feeds and, a fairly good agreement is shown between the predicted cutting forces and test results.

• 유체기계공업학회:학술대회논문집
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• 유체기계공업학회 2004년도 유체기계 연구개발 발표회 논문집
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• pp.754-760
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• 2004

The miniaturization and integration are trend of modern blood analyses. Micro-Bio-Fluidics plays an important role in a micro blood analysis system. In this paper, analysis and design technology for blood analysis system is presented. Numerical simulations of a blood flow in micro separator and reservoir are conducted. As a result, we suggest on-chip micro separator, which performed plasma separation from whole blood in micro channels.

• 한국표면공학회지
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• 제36권2호
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• pp.168-175
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• 2003

The purpose of solder plating on chip external electrode is to provide a proper solderability to chips on PCB's. The quantitative or qualitative analysis of solderability has been performed by destructive methods, reflow or flow. Evidently, the solderability tends to depend on the grain structure which is varied with additives. Research on the feasibility of employing electrochemical techniques to characterize the solderability of electroplated tin - lead, with respect to the additives, was non destructively performed. The deposit morphology and the polarization behavior of electrolytes containing proprietary additives were evaluated to investigate the soldering degradation. The plated panels from synthetic electrolyte were analyzed according to % Sn, plating thickness, deposit appearance, grain structure, solderability and cyclic voltammetry.

• 전자공학회지
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• 제30권9호
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• pp.1002-1011
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• 2003

In this paper, we introduce an integrated SoC front-end design & verification environment which can be practically used in the embedded 32-bit processor-core SoC VLSI design. Our introduced SoC design & verification environment integrates two most important flows, such as the RTL power estimation and code coverage analysis, with the functional verification (chip validation) flow which is used in the conventional simulation-based design. For this, we developed two simulation-based inhouse tools, RTL power estimator and code coverage analyzer, and used them to adopt them to our RTL design and to increase the design quality of that. Our integrated design environment also includes basic design and verification flows such as the gate-level functional verification with back annotation information and test vector capture & replay environment.

• IEIE Transactions on Smart Processing and Computing
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• 제4권2호
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• pp.83-88
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• 2015

Core-A is 32-bit synthesizable processor core with a unique instruction set architecture (ISA). In this paper, the Core-A ISA is introduced with discussion of useful features and the development environment, including the software tool chain and hardware on-chip debugger. Core-A is described using Verilog-HDL and can be customized for a given application and synthesized for an application-specific integrated circuit or field-programmable gate array target. Also, the GNU Compiler Collection has been ported to support Core-A, and various predesigned platforms are well equipped with the established design flow to speed up the hardware/software co-design for a Core-A-based system.

• 한국산업정보학회논문지
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• 제18권1호
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• pp.19-24
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• 2013

As CMOS technology is scaled down more aggressively, the reliability mechanism (or aging effect) caused by the diffusion of metal atoms along the conductor in the direction of the electron flow, also called electromigration (EM), has become a major reliability concern. With the present of EM, it is difficult to control the current flows of the MOSFET device and interconnect. In addition, nanoscale CMOS circuits suffer from increased gate leakage current and power consumption. In this paper, the EM effects on current of the nanoscale CMOS circuits are analyzed. Finally, this paper introduces an on-chip current measurement method providing lifetime electromigration management which are designed using 45-nm CMOS predictive technology model.

• International Journal of Ocean Engineering and Technology Speciallssue:Selected Papers
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• 제3권1호
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• pp.40-48
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• 2000

The term "deep holes" is used to describe the machining of holes with a relatively large length to diameter ratio. The main feature of BTA deep hole drilling is the stabilization of cutting force necessary for the self guidance of the drill head. An additional feature is the cutting tool edges that are unsymmetrically placed on the drill head. There is an increasing necessity to predict the hole geometry and other dynamic stability behavior of deep hole drilling guidance. In this study, the effects of BTA deep hole drilling conditions on the hole profile machined piece are analyzed using domain analysis technique. The profile of deep hole drilled work piece is related to cutting speed, feed rate, chip flow, tool wear, and so on. This study deals with the experimental results obtained during the BTA drilling on SM45C, SM55C carbon steels and SCM440 steels under various cutting conditions, and these results are compared with analytical evaluations.aluations.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2005년도 학술대회 논문집
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• pp.409-414
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• 2005

We are interaction refrigeration warehouse cold water pump system and photovoltaic generation system. At this time, a target pressure is able to control in spite of change of the pressure according to pump head and rate of flow of pump. Also, we carry out the vector control of BLDC moor with the maximum torque operation and a high reliability from territory of each operation speed. Therefore, in this paper, we conclude energy saving technique of refrigeration warehouse cold water pump system.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.1546-1547
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• 2007

휴대용 면역진단 시스템을 구현하기 위하여 설계된 공기주입기로 구동되는 랩온어칩 내의 유체 유동을 컴퓨터 시뮬레이션을 통하여 해석하고, 문제점을 보완할 수 있는 구조로 랩온어칩을 재설계하였다. 공기주입기에서 흘러나오는 공기를 이용해 완충액 저장고 내에 있는 완충액을 토출시킬 때 다량의 기포가 발생함을 시뮬레이션 결과를 통해 알 수 있었다. 완충액 저장고의 내부에 계단형 구조를 삽입함으로서 완충액 이송 시 형성되는 기포를 상당히 억제할 수 있었다. 또한 계단형 구조는 유선을 역행 방지판 쪽으로 분산시켜 역행 방지판의 효율을 높일 것이다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.173-176
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• 1999

Continuing improvement of microprocessor performance involves in the devece size. This allow greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However this has led to propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance(RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. Becase of pattering MSSQ (Methylsilsequioxane), we use RIE(Reactive ton Etching) which is a good anisotrgpy. In this study, according as we control a flow rate of CF$_4$/O$_2$ gas, RF power, we analysis by using ${\alpha}$ -step, SEM and AFM,