• Title/Summary/Keyword: Chip 냉각

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Implementation of BSCT $320{\times}240$ IR-FPA for Uncooled Thermal Imaging System (비냉각 열 영상 시트템용 BSCT $320{\times}240$ IR-FPA의 구현)

  • Kang, Dae-Seok;Shin, Gyeong-Uk;Park, Jae-U;Yoon, Dong-Han;Song, Seong-Hae;Han, Myeong-Su
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.11
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    • pp.7-13
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    • 2002
  • BSCT 320${\times}$240 IRFPA detector module is implemented, which is a key component in uncooled thermal imaging systems. The detector module consists of two parts, infrared sensitive pixel array and read-out integrated circuit(ROIC). The BSCT 320${\times}$240 pixels are made by laser scribe process and 10-${\mu}m$ micro-bump to satisfy 50-${\mu}m$ pitch and 95-% fill-factor. The ROIC has been designed to electrically address the pixels sequentailly and to improve signal-to-noise ratio with single transistor amplifier, HPF, tunable LPF and clamp circuit. The fabricated hybrid chip of detector and ROIC has been mounted on the TEC built-in ceramic package for more stable operation and tested for lots of electrical and optical properties. The IRFA sample has shown successful properties and met with good results of fill-factor, detectivity and responsivity.

Performance-aware Dynamic Thermal Management by Adaptive Vertical Throttling in 3D Network-on-Chip (3D NoC 구조에서 성능을 고려한 어댑티브 수직 스로틀링 기반 동적 열관리 기법)

  • Hwang, Junsun;Han, Tae Hee
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.7
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    • pp.103-110
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    • 2014
  • Recent TSV based 3D Integrated Circuit (IC) technology needs more powerful thermal management techniques. However, because cooling cost and form factor are restricted, thermal management are emphasis on software based techniques. But in case of throttling thermal management which one of the most candidate technique, increasing bus occupation induce total performance decrease. To solve communication bottleneck issue in TSV based 3D SoC, we proposed adaptive throttling technique Experimental results show that the proposed method can improve throughput by about 72% compare with minimal path routing.

Technology Trends of Semiconductor Package for ESG (ESG를 위한 반도체 패키지 기술 트렌드)

  • Minsuk Suh
    • Journal of the Microelectronics and Packaging Society
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    • v.30 no.3
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    • pp.35-39
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    • 2023
  • ESG (Environment, Social, Governance) has become a major guideline for many companies to improve corporate value and enable sustainable management. Among them, the environment requires a technological approach. This is because technological solutions are needed to reduce or prevent environmental pollution and save energy. Semiconductor package technology has been developed to better satisfy the essential roles of semiconductor packaging: chip protection, electrical/mechanical connection, and heat dissipation. Accordingly, technologies have been developed to improve heat dissipation effect, improve electrical/mechanical properties, improve chip protection reliability, stacking and miniaturization, and reduce costs. Among them, heat dissipation technology increases thermal efficiency and reduces energy consumption for cooling. Also, technology to improve electrical characteristics has had an impact on the environment by reducing energy consumption. Technologies that recycling or reducing material consumption reduce environmental pollution. And technologies that replace environmentally harmful substances contribute to environmental improvement, in particular. In this paper, I summarize trends in semiconductor package technologies to prevent pollution and improve environment.

Analysis on the Temperature of Multi-core Processors according to Placement of Functional Units and L2 Cache (코어 내부 구성요소와 L2 캐쉬의 배치 관계에 따른 멀티코어 프로세서의 온도 분석)

  • Son, Dong-Oh;Kim, Jong-Myon;Kim, Cheol-Hong
    • Journal of the Korea Society of Computer and Information
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    • v.19 no.4
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    • pp.1-8
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    • 2014
  • As cores in multi-core processors are integrated in a single chip, power density increased considerably, resulting in high temperature. For this reason, many research groups have focused on the techniques to solve thermal problems. In general, the approaches using mechanical cooling system or DTM(Dynamic Thermal Management) have been used to reduce the temperature in the microprocessors. However, existing approaches cannot solve thermal problems due to high cost and performance degradation. However, floorplan scheme does not require extra cooling cost and performance degradation. In this paper, we propose the diverse floorplan schemes in order to alleviate the thermal problem caused by the hottest unit in multi-core processors. Simulation results show that the peak temperature can be reduced efficiently when the hottest unit is located near to L2 cache. Compared to baseline floorplan, the peak temperature of core-central and core-edge are decreased by $8.04^{\circ}C$, $8.05^{\circ}C$ on average, respectively.

A Study on the Improvement of Machinability in Hot-Forged Aluminum Alloy Product(Al 7075) (알루미늄 합금(Al 7075) 절삭성 향상을 위한 열간단조 후처리 방법에 관한 연구)

  • 김진복;임학진;강범수
    • Journal of the Korean Society of Propulsion Engineers
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    • v.4 no.2
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    • pp.46-53
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    • 2000
  • Hot forging of aluminum alloy has the bad machinability due to continuous chip formation caused from the ductility The bad machinability requires a labor and a high cost to produce final products after hot forging. In industrial field, T4 heat treatment is performed to improve the machinability, and the annealing and the cold sizing are followed. In this study, a series of heat treatments are introduced during hot forging operation without T4 heat treatment after forming so that it improves the machinability with reduction of the number of operations and machining cost. Instead of T4 heat treatment, water cooling and air cooling are tried and compared to find out an optimum cooling condition

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Thermal Management on 3D Stacked IC (3차원 적층 반도체에서의 열관리)

  • Kim, Sungdong
    • Journal of the Microelectronics and Packaging Society
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    • v.22 no.2
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    • pp.5-9
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    • 2015
  • Thermal management becomes serious in 3D stacked IC because of higher heat flux, increased power generation, extreme hot spot, etc. In this paper, we reviewed the recent developments of thermal management for 3D stacked IC which is a promising candidate to keep Moore's law continue. According to experimental and numerical simulation results, Cu TSV affected heat dissipation in a thin chip due to its high thermal conductivity and could be used as an efficient heat dissipation path. Other parameters like bumps, gap filling material also had effects on heat transfer between stacked ICs. Thermal aware circuit design was briefly discussed as well.

Fundamental Design of Cyclone Collector for Oil Mist (오일미스트용 사이클론 집진기에 관한 기초 설계 -오일미스트 및 슬러지 입자 융합연구-)

  • Jang, Sung-Cheol;Ahn, Hwi-Woong;Lee, Chan-Kyu
    • Journal of the Korean Society of Manufacturing Technology Engineers
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    • v.22 no.2
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    • pp.223-227
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    • 2013
  • Dust collecting performance of cyclone collector for oil mist was alalyzed in the study. The purposes of using cutting fluid during cutting have been colling, lubricating, chip washing and anti-corroding. However, the present manufactaring industry restricts the use of cutting fluid because cutting fluid confains poisonous substances which are harmful to the human body. Also, the optimum design oil-mist collector. The new oil mist collector was designed. In the near future, this device must be tested in the real machining center and CNC machine. Cutting using oil-mist showed better cutting characteristics than dry, air and fluid cutting with respect to by cutting force, tool wear and surface roughness. The model(A, B Type cyclone) of the set of fixture and alveolus are made by using a CAE software. Finally, we have obtained a model A Type solution by using orthogonal array. Therefore, it could be confirmed that as the model-A was increased and model-B was decreased, cut diameter was decreased.

Jet Impingement Heat Transfer on a Pedestal Encountered in Chip Cooling (충돌제트를 이용한 pedestal 형상의 칩 냉각연구)

  • Lee, Dae-Hee;Chung, Seung-Hoon;Chung, Young-Suk;Lee, Joon-Sik
    • Proceedings of the KSME Conference
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    • 2001.11b
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    • pp.124-130
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    • 2001
  • The heat transfer and flow measurements were made on a cylindrical pedestal mounted on a flat plate with a turbulent impinging air jet. The heat transfer coefficient distributions on the flat plate were measured using the shroud-transient technique and liquid crystal was used to measure the surface temperature. The jet Reynolds number (Re) is 23,000, the dimensionless nozzle-to-surface distance (L/d) from 2 to 10, the dimensionless pedestal diameter-to-height (H/D) from 0 to 1.5, the dimensionless 2nd pedestal diameter-to-height ($H/D_2$) from 0 to 0.4 and the distance from the stagnation point to 2nd pedestal (p/D). The results show that for H/D = 0.5 to 1.5, the Nusselt number distributions on the plate surface exhibit a maximum between $r/d\;{\cong}\;1.0$ and 1.5. The presence of the pedestal appears to cause the flow separation and reattachment on the plate surface, which results in the maximum heal transfer coefficient. Also, for p/D = 2.5 and $H/D_2$ = 0.3, the local Nusselt number in the region corresponding to $r/d\;{\cong}\;1.1$ was increased up to 50% compared to that for $H/D_2=0$.

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Bolometer-Type Uncooled Infrared Image Sensor Using Pixel Current Calibration Technique (화소 전류 보상 기법을 이용한 볼로미터 형의 비냉각형 적외선 이미지 센서)

  • Kim, Sang-Hwan;Choi, Byoung-Soo;Lee, Jimin;Oh, Chang-woo;Shin, Jang-Kyoo;Park, Jae-Hyoun;Lee, Kyoung-Il
    • Journal of Sensor Science and Technology
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    • v.25 no.5
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    • pp.349-353
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    • 2016
  • Recently, research on bolometer-type uncooled infrared image sensor which is made for industrial applications has been increasing. In general, it is difficult to calibrate fixed pattern noise (FPN) of bolometer array. In this paper, average-current calibration algorithm is presented for reducing bolometer resistance offset. A resistor which is produced by standard CMOS process, on the average, has a deviation. We compensate for deviation of each resistor using average-current calibration algorithm. The proposed algorithm has been implemented by a chip which is consisted of a bolometer pixel array, average current generators, current-to-voltage converters (IVCs), a digital-to-analog converter (DAC), and analog-to-digital converters (ADCs). These bolometer-resistor array and readout circuit were designed and manufactured by $0.35{\mu}m$ standard CMOS process.

A Study on the Application of Thermoelectric Module to the Electric Telecommunication Equipment Cooling (열전소자를 이용한 전자 통신장비 냉각에 관한 연구)

  • Kim, Jong-Soo;Im, Yong-Bin;Kong, Sang-Un
    • Journal of Fisheries and Marine Sciences Education
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    • v.16 no.2
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    • pp.210-217
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    • 2004
  • Cooling technology has been a vital prerequisite for the rapid, if not explosive, growth of the electronic equipment industry. This has been especially true during the last 20 years with the advent of intergrated circuit chips and their applications in computers and related electronic products. The purpose of this study is to develop a telecommunication equipment cooling system using a thermoelectric module combined with cooling fan. Thermoelectric module is a device that can perform cooling only by input of electric power. In the present study, the cooling package using the thermoeletric module has been developed to improve the thermal performance. The cooling characteristics of the electronic chip was placed into the subrack and it can be rapidly assembled or disassembled in the equipment rack. As a preliminary experiment, the cooling performances between a conventional way using a cooling fin and a proposed method applying the thermoelectric module was comosed and analyzyed. The cooling performance at a simulated electronic component packaging a thermomodule operated well.