• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.649-650
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• 2005

반도체는 고집적화, 고속도화, 저전력화를 목적으로 발전하고 있다. 이를 위하여 design rule의 감소, 새로운 물질과 프로세스의 적용 등 많은 연구가 이루어지고 있으며, RC delay time을 줄이기 위한 Cu 와 저유전율 재료의 적용이 그 대표적인 예라 할 수 있다. Cu 배선은 기존의 Al 배선에 비하여 높은 전자이동 (electro-migration)과 응력 이동 (stress-migration) 저항을 가짐으로써 전기적인 성능 (electrical performance) 에서 이점을 가지고 있다. 반도체에서의 Cu 배선 구조는 평탄화된 표면 및 배선들 사이에서의 좋은 전기적인 절연성을 가져야 하며, 이는 디싱(dishing)과 에로젼(erosion)의 중요한 인자가 된다. 기존의 평탄화 공정인 Cu CMP(Chemical Mechanical Polishing)에 있어서 이러한 디싱, 에로전과 같은 결함은 선결되어져야 할 문제로 인식되고 있다. 따라서 본 연구에서는 이러한 결합들을 감소시키기 위한 새로운 평탄화 방법으로 Cu gap-filling 을 하는 동시에 평탄화된 표면을 이루는 ECMD(Electro-Chemical Mechanical Deposition) 공정의 전기적 기계적 특성을 파악하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.276-276
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• 2009

Solar cells has been studied mainly the high efficiency and lower prices. Using recycling wafer as a way to realize their money in it, there is a way to manufacture a solar cell substrate. How to play the recycling wafer, CMP(Chemical Mechanical Polishing) and remelting process is the complex and the expensive equipment. However, using the Micro-Blaster, the process easier, and cheaper prices. Micro-Blaster confirmed that the remaining amount of material left after the process recycling wafer surface.

• Proceedings of the KIEE Conference
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• 2000.11a
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• pp.250-255
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• 2000

본 "수소 플라즈마를 이용한 SOI 기판 제작 및 SOI 전력용 반도체 소자 제작에 관한 연구"를 통해 수소플라즈마 전처리 공정에 의한 실리콘 기판 표면의 활성화를 통해 실리콘 직접 접합 공정을 수행하여 접합된 기판쌍을 제작할 수 있었으며, 접합된 기판쌍에 대한 CMP(Chemical Mechanical Polishing) 공정을 통해 SOI(Silicon on Insulator) 기판을 제작할 수 있었다. 아울러, 소자의 동작 시뮬레이션을 통해 기존 SOI LIGBT(Lateral Insulated Gate Bipolar Transistor) 소자에 비해 동작 특성이 향상된 이중 채널 SOI LIGBT 소자의 설계 파라미터를 도출하였으며, 공정 시뮬레이션을 통해 소자 제작 공정 조건을 확립하였고, 마스크 설계 및 소자 제작을 통해 본 연구 수행으로 개발된 SOI 기판의 전력용 반도체 소자 제작에 대한 가능성을 확인할 수 있었다.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.481-482
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• 2008

In this paper, the advanced process has been presented to remove the WSix peeling that was made in sub 100nm DRAM SRCAT(Sphere-shaped-Recess-Ch annel-Array Transistor). The source of WSix peeling was proved to be the groove of gate poly film. We have completely solved the problems to adopt the gate-poly CMP (Chemical Mechanical Polishing) process.

• Journal of Information Display
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• v.3 no.3
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• pp.35-43
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• 2002

Silicon-based 0.69-inch AMOEL microdisplay with integrated driver and timing controller circuits for microdisplay applications has been developed using 0.35 ${\mu}m$ l-poly 4-metal standard CMOS process with 5 V CMOS devices and CMP (Chemical Mechanical Polishing) technology. To reduce the large data programming time consumed in a conventional current programming pixel circuit technique and to achieve uniform display, de-amplifying current mirror pixel circuit and the current-mode data driver circuit with threshold roltage compensation are proposed. The proposed current-mode data driver circuit is inherently immune to the ground-bouncing effect. The Monte-Carlo simulation results show that the proposed current-mode data driver circuit has channel-to-channel non-uniformity of less than ${\pm}$0.6 LSB under ${\pm}$70 mV threshold voltage variaions for both NMOS and PMOS transistors, which gives very good display uniformity.

• Journal of the Korea Society for Simulation
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• v.11 no.1
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• pp.23-30
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• 2002

An STI(Shallow Trench Isolation) by using a CMP(Chemical Mechanical Polishing) process has been one of the key issues in the device isolation[1] In this paper we fabricated N, P-MOSFEET tall analyse hump characteristics in various rounding oxdation thickness(ex : Skip, 500, 800, 1000$\AA$). As a result we found that hump occurred at STI channel edge region by field oxide recess. and boron segregation(early turn on due to boron segregatiorn at channel edge). Therefore we improved that hump occurrence by increased oxidation thickness, and control field oxide recess( 20nm), wet oxidation etch time(19HF,30sec), STI nitride wet cleaning time(99HF, 60sec+P 90min) and fate pre-oxidation cleaning time (U10min+19HF, 60sec) to prevent hump occurring at STI channel edge.

• Corrosion Science and Technology
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• v.9 no.6
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• pp.276-280
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• 2010

Copper(Cu) as an interconnecting metal layer can replace aluminum (Al) in IC fabrication since Cu has low electrical resistivity, showing high immunity to electromigration compared to Al. However, it is very difficult for copper to be patterned by the dry etching processes. The chemical mechanical polishing (CMP) process has been introduced and widely used as the mainstream patterning technique for Cu in the fabrication of deep submicron integrated circuits in light of its capability to reduce surface roughness. But this process leaves a large amount of residues on the wafer surface, which must be removed by the post-CMP cleaning processes. Copper corrosion is one of the critical issues for the copper metallization process. Thus, in order to understand the copper corrosion problems in post-CMP cleaning solutions and study the effects of DC biases and post-CMP cleaning solution concentrations on the Cu film, a constant voltage was supplied at various concentrations, and then the output currents were measured and recorded with time. Most of the cases, the current was steadily decreased (i.e. resistance was increased by the oxidation). In the lowest concentration case only, the current was steadily increased with the scarce fluctuations. The higher the constant supplied DC voltage values, the higher the initial output current and the saturated current values. However the time to be taken for it to be saturated was almost the same for all the DC supplied voltage values. It was indicated that the oxide formation was not dependent on the supplied voltage values and 1 V was more than enough to form the oxide. With applied voltages lower than 3 V combined with any concentration, the perforation through the oxide film rarely took place due to the insufficient driving force (voltage) and the copper oxidation ceased. However, with the voltage higher than 3 V, the copper ions were started to diffuse out through the oxide film and thus made pores to be formed on the oxide surface, causing the current to increase and a part of the exposed copper film inside the pores gets back to be oxidized and the rest of it was remained without any further oxidation, causing the current back to decrease a little bit. With increasing the applied DC bias value, the shorter time to be taken for copper ions to be diffused out through the copper oxide film. From the discussions above, it could be concluded that the oxide film was formed and grown by the copper ion diffusion first and then the reaction with any oxidant in the post-CMP cleaning solution.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.04b
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• pp.49-49
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• 2009

최근 범세계적인 그린에너지 정책에 관련해 화석연료를 대체할 수 있는 수소, 풍력, 태양광 등의 대체 에너지에 대한 관심이 고조되고 있다. 이러한 여러 대체에너지 중에서도 태양광을 전기에너지로 변환하는 태양전지에 관한 연구가 집중되고 있다. 태양전지는 구조적으로 단순하고 제조 공정도 비교적 간단하지만, 보다 널리 보급되기 위해서는 경제성 향상이라는 문제점을 해결해야 한다. 이를 위해서는 기존의 실리콘 태양전지를 대체할 수 있는 신물질에 대한 연구가 필요하며, 그 중에서도 반도체 기술을 이용한 박막형 태양전지는 기존의 실리콘 태양 전지가 가지고 있는 고비용이라는 문제점을 극복할 수 있을 것으로 기대를 모으고 있다. 박막형 태양전지의 박막 재료로는 CIGS, CdTe 등이 연구되어지고 있지만, 아직까지는 기존의 실리콘 태양전지에 비해 에너지변환효율이 낮은 이유로 인해 실용화가 많이 이루어지지 못하고 있는 것이 사실이다. 이러한 박막형 태양전지의 재료들 중에서도 CdTe는 이종접합 박막형 태양전지에 흡광층으로 사용되는 것으로 상온에서 1.45eV 정도의 밴드갭(band gap) 에너지를 갖는 II-VI족 화합물반도체로써 태양광 스펙트럼과 잘 맞는 이상적인 밴드랩 에너지와 높은 광흡수도 때문에 박막형 태양전지로 가장 주목을 받고 있다. CdTe 박막의 제조 방법으로는 진공증착법(vacuum evaporation), 전착법(electrodeposition), 스퍼터링법(sputtering) 등이 있지만 본 연구에서는 스퍼터링법을 이용하여 박막을 증착하였다. 이상과 같이 증착된 CdTe 박막을 화학적기계적연마(CMP, chemical mechanical polishing) 공정을 적용시킴으로써, 태양전지의 에너지변환효율에 직접적인 영향을 끼칠 수 있는 CdTe 박막의 물리적, 전기적 특성들의 변화를 연구하기 위한 선행 연구를 진행하였다. 특히 본 연구에서는 CdTe 박막의 화학적 기계적 연마 특성을 분석하여 정규화를 통한 모델링을 수행하였다. 또한 화학적기계적연마 공정 전과 후의 표면 특성을 관찰하기 위해 SEM(scanning electron microscopy)과 AFM(atomic forced microscope)를 이용하였으며, 구조적 특성 관찰을 XRD(X-ray diffraction)를 사용하여 실험을 수행하였다.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.1
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• pp.39-45
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• 2012

Three-dimensional integrated circuit(3D IC) technology has become increasingly important due to the demand for high system performance and functionality. In this work, BOE and HF wet etching of Cu line surfaces after CMP were conducted for Cu-Cu pattern direct bonding. Step height of Cu and $SiO_2$ as well as Cu dishing after Cu CMP were analyzed by the 3D-Profiler. Step height increased and Cu dishing decreased with increasing BOE and HF wet etching times. XPS analysis of Cu surface revealed that Cu surface oxide layer was partially removed by BOE and HF wet etching treatment. BOE treatment showed not only the effective $SiO_2$ etching but also reduced dishing and Cu surface oxide rather than HF treatment, which can be used as an meaningful process data for reliable Cu-Cu pattern bonding characteristics.

• Analytical Science and Technology
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• v.32 no.5
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• pp.173-184
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• 2019

As the size of semiconductors becomes smaller, it is necessary to perform high precision polishing of nanoscale. Ceria, which is generally used as an abrasive, is widely used because of its uniform quality, but its stability is not high because it has a high molecular weight and causes agglomeration and rapid precipitation. Such agglomeration and precipitation causes scratches in the polishing process. Therefore, it is important to accurately analyze the size distribution of ceria particles. In this study, a study was conducted to select dispersants useful for preventing coagulation and sedimentation of ceria. First, a dispersant was synthesized and a ceria slurry was prepared. The defoamer selection experiment was performed in order to remove the air bubbles which may occur in the production of ceria slurry. Dynamic light scattering (DLS) and asymmetrical flow field-flow fractionation (AsFlFFF) were used to determine the size distribution of ceria particles in the slurry. AsFlFFF is a technique for separating nanoparticles based on sequential elution of samples as in chromatography, and is a useful technique for determining the particle size distribution of nanoparticle samples. AsFlFFF was able to confirm the presence of a little quantities of large particles in the vicinity of 300 nm, which DLS can not detect, besides the main distribution in the range of 60-80 nm. AsFlFFF showed better accuracy and precision than DLS for particle size analysis of a little quantities of large particles such as ceria slurry treated in this study.