• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05c
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• pp.223-227
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• 2002

As the channel length of device shrinks below $0.13{\mu}m$, CMP(chemical mechanical polishing) process got into key process for global planarization in the chip manufacturing process. The removal rate and non-uniformity of the CMP characteristics occupy an important position to CMP process control. Especially, the post-CMP thickness variation depends on the device yield as well as the stability of subsequent process. In this paper, every wafer polished two times for the improvement of oxide CMP process characteristics. Then, we discussed the removal rate and non-uniformity characteristics of post-CMP process. As a result of CMP experiment, we have obtained within-wafer non-uniformity (WIWNU) below 4 [%], and wafer-to-wafer non-uniformity (WTWNU) within 3.5 [%]. It is very good result, because the reliable non-uniformity of CMP process is within 5 [%].

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.125-128
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• 2004

Chemical Mechanical Polishing(CMP) in semiconductor production is characterized its output property by Removal Rate(RR) and Non-Uniformity(NU). Some Previous works shows that RR is determined by production of pressure and velocity and NC is also largely affected by velocity of flow-field during CMP. This study is about the direct measurement of velocity of slurry during CMP and reconstruction whole flow-field by Particle Image Velocimetry(PIV) Techniques. Typical PIV system is tuned adequately for inspecting CMP and Slurry Flow-field is measured by changing both Pad RPM and Carrier RPM. The results show that velocity is majorly determined not by Carrier RPM, but by Pad RPM.

• Transactions on Electrical and Electronic Materials
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• v.2 no.3
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• pp.24-27
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• 2001

The end point of oxide chemical mechanical polishing (CMP) have determined by polishing time calculated from removal rate and target thickness of oxide. This study is about control of oxide removal amounts on the shallow trench isolation (STI) patterned wafers using removal rate and thickness of blanket (non-patterned) wafers. At first, it was investigated the removal properties of PETEOS blanket wafers, and then it was compared with the removal properties and the planarization (step height) as a function of polishing time of the specific STI patterned wafers. We found that there is a relationship between the oxide removal amounts of blanket and patterned wafers. We analyzed this relationship, and the post CMP thickness of patterned wafers could be controlled by removal rate and removal target thickness of blanket wafers. As the result of correlation analysis, we confirmed that there was the strong correlation between patterned and blanket wafer (correlation factor: 0.7109). So, we could confirm the repeatability as applying for STI CMP process from the obtained linear formula. As the result of repeatability test, the differences of calculated polishing time and actual polishing time was about 3.48 seconds. If this time is converted into the thickness, then it is from 104 $\AA$ to 167 $\AA$. It is possible to be ignored because process margin is about 1800 $\AA$.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 1999.11a
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• pp.263-268
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• 1999

Langasite, a new piezoelectric material was polished by CMP(chemical mechanical polishing). To enhance the polishing rate, alumina abrasives were added to commercial ILD1300 slurry which contains silica abrasive. The effect of added alumina 0 the silica slurry on the polishing rate and damage of langasite was investigated, Experimental results show that the polishing rate and roughness increases with increasing added alumina particle size, Crystallinity of the langasite is also lowered by alumina addition.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.370-373
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• 2003

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Chemical-Mechanical Planarization(CMP) of conductors is a key process in Damascene patterning of advanced interconnect structure. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. Electroplated copper depostion is a mature process from a historical point of view, but a very young process from a CMP persperspective. While copper electrodepostion has been used and stuidied for dacades, its application to Cu damascene wafer processing is only now ganing complete accptance in the semiconductor industry. The polishing mechanism of Cu CMP process has been reported as the repeated process of passive layer formation by oxidizer and abrasion action by slurry abrasives. however it is important to understand the effect of oxidizer on copper pasivation layer in order to obtain higher removal rate and non-uniformity during Cu-CMP process. In this paper, we investigated the effects of oxidizer on Cu-CMP process regarding the additional volume of oxidizer.

• Proceedings of the KSME Conference
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• 2003.04a
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• pp.1296-1301
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• 2003

The chemical mechanical polishing(CMP) is necessarily applied to manufacturing the dielectric layer and metal line in the semiconductor device. The conditioning of polishing pad in CMP process additionally operates for maintaining the removal rate, within wafer non-uniformity, and wafer to wafer non-uniformity. But the fixed abrasive pad(FAP) using the hydrophilic polymer with abrasive that has the swelling characteristic by water owns the self-conditioning advantage as compared with the general CMP. FAP also takes advantage of planarity, resulting from decreasing pattern selectivity and defects such as dishing due to the reduction of abrasive concentration. This paper introduces the manufacturing technique of FAP. And the tungsten CMP using FAP achieved the good conclusion in point of the removal rate, non-uniformity, surface roughness, material selectivity, micro-scratch free contemporary with the pad life-time.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.10
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• pp.812-816
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• 2000

It is very important to understand the correlation of between inter dielectric(ILD) CMP process and various facility factors supplied to equipment to equipment system. In this paper, the correlation between the various facility factors supplied to CMP equipment system and ILD-CMP process was studied. To prevent the partial over-polishing(edge hot-spot) generated in the wafer edge area during polishing, we analyze various facilities supplied at supply system. With facility shortage of D.I water(DIW) pressure, we introduced an adding purified $N_2$(P$N_2$)gas in polishing head cleaning station for increasing a cleaning effect. DIW pressure and P$N_2$gas factors were not related with removal rate, but edge hot-spot of patterned wafer had a serious relation. We estimated two factors (DIW pressure and P$N_2$gas) for the improvement of CMP process. Especially, we obtained a uniform planarity in patterned wafer and prohibited more than 90% wafer edge over-polishing. In this study, we acknowledged that facility factors supplied to equipment system played an important role in ILD-CMP process.

• Journal of the Korean Chemical Society
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• v.57 no.1
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• pp.159-164
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• 2013

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.39-42
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• 2002

Recently, CMP (chemical mechanical polishing) technology has been widely used for global planarization of multi-level interconnection for ULSI applications. However, COO (cost of ownership) and COC (cost of consumables) were relatively increased because of expensive slurry. In this paper, we have studied the possibility of recycle of reused silica slurry in order to reduce the costs of CMP slurry. The post-CMP thickness and within-wafer non-uniformity(WIWNU) were measured as a function of different slurry composition. As a experimental result, the performance of reused slurry with annealed silica abrasive of 2 wt% contents was showed high removal rate and low non-uniformity. Therefore, we propose two-step CMP process as follows In the first-step CMP, we can polish the thick and rough film surface using remaked slurry, and then, in the second-step CMP, we can polish the thin film and fine pattern using original slurry. In summary, we can expect the saving of high costs of slurry.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.9
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• pp.759-764
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• 2003

Recently, CMP (chemical mechanical polishing) technology has been widely used for global planarization of multi-level interconnection for ULSI applications. However, COO (cost of ownership) and COC (cost of consumables) were relatively increased because of expensive slurry. In this paper, we have studied the possibility of recycle of roused silica slurry in order to reduce the costs of CMP slurry. The post-CMP thickness and within-wafer non-uniformity (WIWNU) wore measured as a function of different slurry composition. As an experimental result, the performance of reused slurry with annealed silica abrasive of 2 wt％ contents was showed high removal rate and low non-uniformity. Therefore, we propose two-step CMP process as follows , In tile first-step CMP, we can polish the thick and rough film surface using remaked slurry, and then, in the second-step CMP, we can polish the thin film and fine pattern using original slurry. In summary, we can expect the saying of high costs of slurry.