• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.12
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• pp.1084-1090
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• 1998

As device sizes are scaled down to submicron dimensions, planarization technology becomes increasingly important for both device fabrication and formation of multilevel interconnects. Chemical mechanical polishing (CMP) has emerged recently as a new processing technique for achieving a high degree of planarization for submicron VLSI applications. The polishing process has many variables, and most of which are not well understood. The factors determine the planarization performance are slurry and pad type, insert material, conditioning technique, and choice of polishing tool. Circuit density, pattern size, and wiring layout also affect the performance of a CMP planarization process. This paper presents the results of studies on CMP process window characterization for 0.35 micron process with 5 metal layers.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.7
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• pp.311-315
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• 2002

Chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD), inter-level dielectric (ILD) layers of multi-layer interconnections. In this paper, we studied the characteristics of polishing pad, which can apply shallow trench isolation (STI)-CMP process for global planarization of multi-level interconnection structure. Also, we investigated the effects of different sets of polishing pad, such as soft and hard pad. As an experimental result, hard pad showed center-fast type, and soft pad showed edge-fast type. Totally, the defect level has shown little difference, however, the counts of scratch was detected less than 2 on JR111 pad. Through the above results, we can select optimum polishing pad, so we can expect the improvements of throughput and device yield.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1997.11a
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• pp.456-460
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• 1997

As device sizes are scaled to submicron dimensions, planarization technology becomes increasing1y important, both during device fabrication and during formation of multilevel interconnects and wiring. Chemical Mechanical Polishing (CMP) has emerged recently as a new processing technique for achieving a high degree of planarization for submicron VLSI applications. This paper is presented the results of CMP process window characterization studies for 0.35 micron process with 6 metal layers.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2002.10b
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• pp.435-437
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• 2002

Polishing of copper, a process called copper chemical mechanical polishing, is a critical, intermediate step in the planarization of silicon wafers. During polishing, the electrodeposited copper films are removed by slurries: and the differential polishing rates between copper and the surrounding silicon dioxide leads to a greater removal of the copper. The differential polishing develops dimples and furrows; and the process is called dishing and erosion. In this work, we present the results of experiments on dishing and erosion of copper-CMP, using patterned silicon wafers. Results are analyzed for the pattern factors and properties of the copper layers. Three types of pads - plain, perforated, and grooved - were used for polishing. The effect of slurry chemistries and pad soaking is also reported.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.11a
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• pp.172-176
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• 1996

The rapid structural change of ULSI chip includes minimum features, multilevel interconnection and large diameter wafers. Demands for the advanced chip structure necessitates the development of enhanced deposition, etching and planarization techniques. Planarization refers to a process that make rugged surfaces flat and uniform. One of the emerging technologies for planarization is chemical mechanical polishing(CMP). Chemical and mechanical removal actions occur during CMP, and both appear to be closely interrelated. The purpose of this study is the optimal application of the slurry to the various types of device materials during CMP. We investigates the effect of slurry on CMP characteristics for thermal oxide and sputtered Al blanket wafers. Results from the polishing rate and the uniformity of residual film include mechanical and chemical reactions between several set of slurry and work material.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.10
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• pp.441-446
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• 2003

The chemical mechanical polishing (CMP) process is now widely employed in the ultra large scale integrated (ULSI) semiconductor fabrication. Especially, shallow trench isolation (STI) has become a key isolation scheme for sub-0.13/0.10${\mu}{\textrm}{m}$ CMOS technology. The most important issues of STI-CMP is to decrease the various defects such as nitride residue, dishing, and tom oxide. To solve these problems, in this paper, we studied the planarization characteristics using slurry additive with the high selectivity between $SiO_2$ and $Si_3$$N_4$ films for the purpose of process simplification and in-situ end point detection. As our experimental results, it was possible to achieve a global planarization and STI-CMP process could be dramatically simplified. Also, we estimated the reliability through the repeated tests with the optimized process conditions in order to identify the reproducibility of STI-CMP process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.10
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• pp.838-843
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• 2002

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The reverse moat etch process has been used for the shallow trench isolation(STI)-chemical mechanical polishing(CMP) process with conventional low selectivity slurries. Thus, the process became more complex, and the defects were seriously increased. In this paper, we studied the direct STI-CMP process without reverse moat etch step using high selectivity slurry(HSS). As our experimental results show, it was possible to achieve a global planarization without the complicated reverse moat process, the STI-CMP process could be dramatically simplified, and the defect level was reduced. Therefore the throughput, yield, and stability in the ULSI semiconductor device fabrication could be greatly improved.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.10a
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• pp.56-56
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• 2003

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.10a
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• pp.935-938
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• 1997

Recently, the minimum line width shows a tendency to decrease and the multi-level increase in semiconductor. Therefore, a planarization technique is needed and chemical mechanical polishing(CMP) is considered as one of the most suitable process. CMP accomplishes a high polishing performance and a global planarization of high quality. But there are several defects in CMP such as micro-scratches, abrasive contaminations, and non-uniformity of polished wafer edges. Wet etching include of Spin-etching can improve he defects of CMP. It uses abrasive-free chemical solution instead of slurry. On this study, ILD(INterlayer-Dielectric) was removed by CMP and wet-etching methods in order to investigate the superiority of wet etching mechanism. In the thin film wafer, the results were evaluated at a viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU). And pattern step height was also compared for planarization characteristics of the patterned wafer.

• KSTLE International Journal
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• v.5 no.1
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• pp.32-35
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• 2004

The purpose of this study is to investigate the effects of the structure and mechanical properties of laser-processed pads on their polishing behavior such as their removal rate and WIWNU (within wafer non-uniformity) during the chemical mechanical planarization (CMP) process. The holes on the pad acted as the reservoir of slurry particles and enhanced the removal rate. Without grooves, no effective removal of wafers was possible. When the length of the circular-type grooves was increased, higher removal rates and lower wafer non-uniformity were measured. The removal rate and non-uniformity linearly increased as the elastic modulus of the top pad increased. Higher removal rates and lower non-uniformity were measured as the hardness of the pad increased.