Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference (한국전기전자재료학회:학술대회논문집)

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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Planarization of Multi-level metal Structure by Chemical Mechanical Polishing

CMP 공정을 이용한 Multilevel Metal 구조의 평탄화 연구

  • 김상용 (중앙대학교 전기공학과) ;
  • 서용진 (대불대학교 전기전자공학부) ;
  • 김태형 (여주전문대 전기과) ;
  • 이우선 (조선대학교 전기 공학과) ;
  • 김창일 (중앙대학교 전기공학과)
  • Published : 1997.11.01
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Abstract

As device sizes are scaled to submicron dimensions, planarization technology becomes increasing1y important, both during device fabrication and during formation of multilevel interconnects and wiring. Chemical Mechanical Polishing (CMP) has emerged recently as a new processing technique for achieving a high degree of planarization for submicron VLSI applications. This paper is presented the results of CMP process window characterization studies for 0.35 micron process with 6 metal layers.

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