• 제목/요약/키워드: Chemical mechanical planarization

검색결과 231건 처리시간 0.026초

슬러리 및 패드 변화에 따른 기계화학적인 연마 특성 (Chemical Mechanical Polishing Characteristics with Different Slurry and Pad)

  • 서용진;정소영;김상용
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제52권10호
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    • pp.441-446
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    • 2003
  • The chemical mechanical polishing (CMP) process is now widely employed in the ultra large scale integrated (ULSI) semiconductor fabrication. Especially, shallow trench isolation (STI) has become a key isolation scheme for sub-0.13/0.10${\mu}{\textrm}{m}$ CMOS technology. The most important issues of STI-CMP is to decrease the various defects such as nitride residue, dishing, and tom oxide. To solve these problems, in this paper, we studied the planarization characteristics using slurry additive with the high selectivity between $SiO_2$ and $Si_3$$N_4$ films for the purpose of process simplification and in-situ end point detection. As our experimental results, it was possible to achieve a global planarization and STI-CMP process could be dramatically simplified. Also, we estimated the reliability through the repeated tests with the optimized process conditions in order to identify the reproducibility of STI-CMP process.

Cu ECMP 공정에서의 전해질 특성평가 (Characterization of Electrolyte in Electrochemical Mechanical Planarization)

  • 권태영;김인권;박진구
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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    • pp.57-58
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    • 2006
  • Chemical-mechanical planarization (CMP) of Cu has used currently in semiconductor process for multilevel metallization system. This process requires the application of a considerable down-pressure to the sample in the polishing, because porous low-k films used in the Cu-multilevel interconnects of 65nm technology node are often damaged by mechanical process. Also, it make possible to reduce scratches and contaminations of wafer. Electrochemical mechanical planarization (ECMP) is an emerging extension of CMP. In this study, the electrochemical mechanical polisher was manufactured. And the static and dynamic potentiodynamic curve of Cu were measured in KOH based electrolyte and then the suitable potential was found.

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Effect of Citric Acid in Cu Chemical Mechanical Planarization Slurry on Frictional Characteristics and Step Height Reduction of Cu Pattern

  • Lee, Hyunseop
    • Tribology and Lubricants
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    • 제34권6호
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    • pp.226-234
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    • 2018
  • Copper chemical mechanical planarization (CMP) has become a key process in integrated circuit (IC) technology. The results of copper CMP depend not only on the mechanical abrasion, but also on the slurry chemistry. The slurry used for Cu CMP is known to have greater chemical reactivity than mechanical material removal. The Cu CMP slurry is composed of abrasive particles, an oxidizing agent, a complexing agent, and a corrosion inhibitor. Citric acid can be used as the complexing agent in Cu CMP slurries, and is widely used for post-CMP cleaning. Although many studies have investigated the effect of citric acid on Cu CMP, no studies have yet been conducted on the interfacial friction characteristics and step height reduction in CMP patterns. In this study, the effect of citric acid on the friction characteristics and step height reduction in a copper wafer with varying pattern densities during CMP are investigated. The prepared slurry consists of citric acid ($C_6H_8O_7$), hydrogen peroxide ($H_2O_2$), and colloidal silica. The friction force is found to depend on the concentration of citric acid in the copper CMP slurry. The step heights of the patterns decrease rapidly with decreasing citric acid concentration in the copper CMP slurry. The step height of the copper pattern decreases more slowly in high-density regions than in low-density regions.

화학기계적폴리싱(CMP)에 의한 층간절연막의 광역평탄화에 관한 연구 (A Global Planarization of Interlayer Dielectric Using Chemical Mechanical Polishing for ULSI Chip Fabrication)

  • 정해도
    • 한국정밀공학회지
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    • 제13권11호
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    • pp.46-56
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    • 1996
  • Planarization technique is rapidly recognized as a critical step in chip fabrication due to the increase in wiring density and the trend towards a three dimensional structure. Global planarity requires the preferential removal of the projecting features. Also, the several materials i.e. Si semiconductor, oxide dielectric and sluminum interconnect on the chip, should be removed simultaneously in order to produce a planar surface. This research has investihgated the development of the chemical mechanical polishing(CMP) machine with uniform pressure and velocity mechanism, and the pad insensitive to pattern topography named hard grooved(HG) pad for global planarization. Finally, a successful result of uniformity less than 5% standard deviation in residual oxide film and planarity less than 15nm in residual step height of 4 inch device wafer, is achieved.

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DHF를 적용한 웨이퍼의 층간 절연막 평탄화에 관한 연구 (A Study on ILD(Interlayer Dielectric) Planarization of Wafer by DHF)

  • 김도윤;김형재;정해도;이은상
    • 한국정밀공학회지
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    • 제19권5호
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    • pp.149-158
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    • 2002
  • Recently, the minimum line width shows a tendency to decrease and the multi-level increases in semiconductor. Therefore, a planarization technique is needed and chemical mechanical polishing(CMP) is considered as one of the most suitable process. CMP accomplishes a high polishing performance and a global planarization of high quality. However there are several defects in CMF, such as micro-scratches, abrasive contaminations and non-uniformity of polished wafer edges. Wet etching process including spin-etching can eliminate the defects of CMP. It uses abrasive-free chemical solution instead of slurry. On this study, ILD(Interlayer-Dielectric) was removed by CMP and wet etching process using DHF(Diluted HF) in order to investigate the possibility of planrization by wet etching mechanism. In the thin film wafer, the results were evaluated from the viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU). And the pattern step heights were also compared for the purpose of planarity characterization of the patterned wafer. Moreover, Chemical polishing process which is the wet etching process with mechanical energy was introduced and evaluated for examining the characteristics of planarization.

전기화학 기계적 연마를 이용한 Cu 배선의 평탄화 (Planarizaiton of Cu Interconnect using ECMP Process)

  • 정석훈;서헌덕;박범영;박재홍;정해도
    • 한국전기전자재료학회논문지
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    • 제20권3호
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    • pp.213-217
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    • 2007
  • Copper has been used as an interconnect material in the fabrication of semiconductor devices, because of its higher electrical conductivity and superior electro-migration resistance. Chemical mechanical polishing(CMP) technique is required to planarize the overburden Cu film in an interconnect process. Various problems such as dishing, erosion, and delamination are caused by the high pressure and chemical effects in the Cu CMP process. But these problems have to be solved for the fabrication of the next generation semiconductor devices. Therefore, new process which is electro-chemical mechanical polishing(ECMP) or electro-chemical mechanical planarization was introduced to solve the technical difficulties and problems in CMP process. In the ECMP process, Cu ions are dissolved electrochemically by the applying an anodic potential energy on the Cu surface in an electrolyte. And then, Cu complex layer are mechanically removed by the mechanical effects between pad and abrasive. This paper focuses on the manufacturing of ECMP system and its process. ECMP equipment which has better performance and stability was manufactured for the planarization process.

습식 에칭에 의한 웨이퍼의 층간 절연막 가공 특성에 관한 연구 (A Study on a Wet etching of ILD (Interlayer Dielectric) Film Wafer)

  • 김도윤;김형재;정해도;이은상
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 1997년도 추계학술대회 논문집
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    • pp.935-938
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    • 1997
  • Recently, the minimum line width shows a tendency to decrease and the multi-level increase in semiconductor. Therefore, a planarization technique is needed and chemical mechanical polishing(CMP) is considered as one of the most suitable process. CMP accomplishes a high polishing performance and a global planarization of high quality. But there are several defects in CMP such as micro-scratches, abrasive contaminations, and non-uniformity of polished wafer edges. Wet etching include of Spin-etching can improve he defects of CMP. It uses abrasive-free chemical solution instead of slurry. On this study, ILD(INterlayer-Dielectric) was removed by CMP and wet-etching methods in order to investigate the superiority of wet etching mechanism. In the thin film wafer, the results were evaluated at a viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU). And pattern step height was also compared for planarization characteristics of the patterned wafer.

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전력 소자용 후막 구리 구조물의 평탄화 (Planarization technology of thick copper film structure for power supply)

  • 주석배;정석훈;이현섭;김형재;정해도
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2007년도 추계학술대회 논문집
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    • pp.523-524
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    • 2007
  • This paper discusses the planarization process of thick copper film structure used for power supply device. Chemical mechanical polishing(CMP) has been used to remove a metal film and obtain a surface planarization which is essential for the semiconductor devices. For the thick metal removal, however, the long process time and other problems such as dishing, delamination and metal layer peeling are being issued, Compared to the traditional CMP process, Electro-chemical mechanical planarization(ECMP) is suggested to solve these problems. The two-step process composed of the ECMP and the conventional CMP is used for this experiment. The first step is the removal of several tens ${\mu}m$ of bulk copper on patterned wafer with ECMP process. The second step is the removal of residual copper layer aimed at a surface planarization. For more objective comparison, the traditional CMP was also performed. As an experimental result, total process time and process defects are extremely reduced by the two-step process.

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기계화학적 연마를 이용한 트렌치 구조의 산화막 평탄화 (Oxide Planarization of Trench Structure using Chemical Mechanical Polishing(CMP))

  • 김철복;김상용;서용진
    • 한국전기전자재료학회논문지
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    • 제15권10호
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    • pp.838-843
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    • 2002
  • Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The reverse moat etch process has been used for the shallow trench isolation(STI)-chemical mechanical polishing(CMP) process with conventional low selectivity slurries. Thus, the process became more complex, and the defects were seriously increased. In this paper, we studied the direct STI-CMP process without reverse moat etch step using high selectivity slurry(HSS). As our experimental results show, it was possible to achieve a global planarization without the complicated reverse moat process, the STI-CMP process could be dramatically simplified, and the defect level was reduced. Therefore the throughput, yield, and stability in the ULSI semiconductor device fabrication could be greatly improved.