• Journal of Information Display
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• 제9권2호
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• pp.9-13
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• 2008

A novel push-pull voltage converter structure, using a switched capacitor type voltage doubler, is proposed. The circuit is constructed with a two-stage push-pull voltage doubler that has a stable operation with small output ripple. The two-stage voltage doubler creates the output voltage 4Vdd. The high clock signal is cross-coupled to the input of the second stage with the opposite phase to reduce two switching transistors and capacitors. Simulation results verify that even with a reduced number of transistor and capacitor, there is no circuit performance loss. Adding one capacitor and two switching transistors the circuit can be changed to eight times of Vdd maker.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.241-246
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40 $M{\sim}725$ MHz with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2011년도 추계학술대회
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• pp.425-428
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• 2011

본 논문에서는 간단한 Maximum Power Point Tracking이 적용된 micro-scale의 빛에너지 하베스팅 회로를 제안한다. 에너지 변환기로는 온칩 PV cell 대신 이와 비슷한 출력을 하는 초소형 PV cell을 사용하였다. 적용된 MPPT는 PV cell의 개방전압($V_{OC}$)와 MPP전압($V_{MPP}$)과의 관계를 이용하였고 이는 pilot PV cell을 이용함으로써 가능하였다. 설계결과 MPPT control을 적용했을 때 부하가 큰 경우에도 대략 $V_{MPP}$ 전압을 부하에 공급함으로써 부하에 연결된 회로가 정상적으로 동작하는 것을 확인하였다. 제안된 회로는 TSMC 0.18um CMOS 공정으로 설계되었다.

• 전기전자학회논문지
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• 제24권3호
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• pp.853-858
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• 2020

본 논문은 통신기기에서 유입 되는 RF 노이즈에 대해 내성을 가진 OLED용 2-채널 DC-DC 변환기를 제안한다. RF 신호 내성을 위해, 입력전압 변동만큼 감쇠시키는 입력전압 변동감쇠 회로가 내장된다. 양의 전압 V_POS를 출력하는 부스트 변환기는 SPWM-PWM 듀얼모드로 동작하고, 데드 타임을 제어함으로써 전력 효율을 제고한다. V_NEG를 출력하는 인버팅 차지펌프는 2-상 출력 구조로 VCO를 이용한 PFM으로 동작해 작은 리플을 갖도록 설계된다. 0.18 ㎛ BCDMOS 공정으로 시뮬레이션 한 결과, 부스트 변환기 출력전압의 오버슈트와 언더슈트는 10 mV에서 각각 2 mV, 5 mV로 감소하였다. 또한, 2-채널 DC-DC 변환기의 전력효율은 39%~93%을 가졌고, 데드 타임 제어기를 적용한 부스트 변환기의 효율은 종전보다 최대 3% 증가하였다.

• 한국전자통신학회논문지
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• 제4권4호
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• pp.247-252
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• 2009

본 논문은 전하펌프와 클록트리거 회로를 사용하는 프리스케일러가 포함된 UHF RFID 응용을 위한 900MHz Integer-N 방식의 주파수 합성기를 소개한다. 쿼드러처 출력이 가능한 전압제어발진기와 프리스케일러, 위상주파수검출기와 전하펌프 및 아날로그 고정 검출기는 0.35-${\mu}m$ CMOS 공정으로 설계되었다. 주파수 분주기는 verilog-HDL 모듈을 통해 설계되었으며 mixed-mode 시뮬레이션을 통해 디자인을 검증하였다. 전압제어발진기의 동작 주파수영역은 828MHz에서 960MHz이고 위상이 90도 차이나는 쿼드러처 신호를 출력한다. 시뮬레이션 결과로 위상잡음은 100KHz offset 주파수에서 -102dBc/Hz 이었으며, 고착시간은 896MHz에서 928MHz까지 32MHz step을 천이할 때 4us이다.

• Journal of electromagnetic engineering and science
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• 제11권2호
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• pp.105-112
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• 2011

In phase-locked frequency synthesizers, a fast-lock technique is frequently employed to overcome the trade-off between a lock-time and a spurious response. The function of fast-lock in a conventional PLL (Phased Lock Loop) IC (Integrated Circuit) is limited by a factor of 16, which is usually implemented by a scaling of charge pumper, and consequently a lock time improvement of a factor of 4 is possible using the conventional PLL IC. In this paper, we propose a novel external active fast-lock loop filter. The proposed loop filter provides, conceptually, an unlimited scaling of charge pumper current, and can overcome conventional trade-off between lock-time and spur suppression. To demonstrate the validity of our proposed loop-filter, we fabricated an X-band frequency synthesizer using the proposed loop filter. The loop filter in the synthesizer is designed to have a loop bandwidth of 100 kHz in the fast-lock mode and a loop bandwidth of 5 kHz in the normal mode, which corresponds to a charge pumper current change ratio of 400. The X-band synthesizer shows successful performance of a lock-time of below 10 ${\mu}sec$ and reference spur suppression below -64 dBc.

• IEIE Transactions on Smart Processing and Computing
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• 제4권3호
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• pp.141-144
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• 2015

A broadband radio frequency synthesizer for multi-band, multi-standard mobile DTV tuners is proposed, it's loop bandwidth can be calibrated to optimize integrated phase noise performance without the problem of phase noise peaking. For this purpose, we proposed a new third-order scalable loop filter and a scalable charge pump circuit to minimize the variation in phase margin during calibration. The prototype phase-lock loop is fabricated in 180nm complementary metal-oxide semiconductor shows that it effectively prevents phase noise peaking from growing while the loop bandwidth increases by up to three times.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 B
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• pp.1202-1205
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• 2000

Germicidal lamps efficiently emit a large amount of ultraviolet rays 253.7nm which have excellent germicidal effect. The lamps are primarily useful for sterilization of air, the surface of various materials and water or liquid. In this paper, analysis of the charge pump power factor correction inverter for driving a 65W UV lamp and electrical characteristics of the lamp are discussed. The operation of the inverter circuit. in which the lamp is included as a load, is analyzed. Experimental results of the inverter circuit are also presented.

• ETRI Journal
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• 제33권6호
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• pp.880-886
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• 2011

With the introduction of high-current 8-inch solar cells, conventional Schottky bypass diodes, usually adopted in photovoltaic (PV) panels to prevent the hot spot phenomenon, are becoming ineffective as they cause relatively high voltage drops with associated undue power consumption. In this paper, we present the architecture of an active circuit that reduces the aforementioned power dissipation by profitably replacing the bypass diode through a power MOS switch with its embedded driving circuitry. Experimental prototypes were fabricated and tested, showing that the proposed solution allows a reduction of the power dissipation by more than 70% compared to conventional Schottky diodes. The whole circuit does not require a dedicated DC power and is fully compatible with standard CMOS technologies. This enables its integration, even directly on the panel, thereby opening new scenarios for next generation PV systems.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -2
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• pp.969-972
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• 2000

This paper proposes 1.5V-3GHz CMOS PLL with a new delay cell for operating in high frequency and multi chained two stage VCO to improve phase noise performance. The proposed multi-chained architecture is able to reduce a timing jitter or a transition spacing and the newly VCO is operating in high frequency. The PFD circuit designed to prevent fluctuation of charge pump circuit under the locking condition. Simulation results show that the tuning range of proposed VCO is wide at 1.8GHz-3.2Ghz and power dissipation is 0.6mW.