• Title/Summary/Keyword: Channel thickness

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A Study on the Performance Analysis of Mobile Fuel Cell (모바일용 연료전지의 성능해석에 관한 연구)

  • Kim, Kwang-Soo;Choi, Jong-Pil;Jeong, Chang-Ryeol;Jang, Jae-Hyeok;Jeon, Byeong-Hee;Kim, Byeong-Hee
    • Journal of the Korean Society for Precision Engineering
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    • v.25 no.1
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    • pp.115-121
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    • 2008
  • In this paper, a three-dimensional computational fluid dynamic model of a proton exchange membrane fuel cell(PEMFC) with serpentine flow channel is presented. A steady state, single phase and isothermal numerical model has been established to investigate the influence of the GDL (Gas Diffusion Layer) parameters. The GDL is made of a porous material such as carbon cloth, carbon paper or metal wire mesh. For the simplicity, the GDL is modeled as a block of material having numerous pathways through which gaseous reactants and liquid water can pass. The porosity, permeability and thickness of the GDL, which are employed in the model parameters significantly affect the PEMFC performance at the high current region.

A Study on the I-V characteristics of a delta doped short-channel HEMT (단채널 덱타도핑 HEMT의 전압-전류 특성에 대한 2차원적 해석)

  • 이정호;채규수;김민년
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.5 no.4
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    • pp.354-358
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    • 2004
  • In this thesis, an analytical model for Ⅰ-Ⅴ characteristics of an n-AlGaAs/GaAs Delta doped HEMT is proposed. 2-dimensional electron gas density, and conduction band edge profile are calculated from a self-consistent iterative solution of the Poisson equation. Parameters, e.g., the saturation velocity, 2-dimensional electron gas concentration, thickness of the doped and undoped layer(AlGaAs, GaAs, spacer etc.,) are in good agreement with the independent calculations.

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A Study on the High Integrated 1TC SONOS flash Memory (고집적화된 1TC SONOS 플래시 메모리에 관한 연구)

  • 김주연;김병철;서광열
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.16 no.5
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    • pp.372-377
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    • 2003
  • To realize a high integrated flash memory utilizing SONOS memory devices, the NOR type ITC(one Transistor Cell) SONOS flash arrays are fabricated and characterized. This SONOS flash arrays with the common source lines are designed and fabricated by conventional 0.35$\mu\textrm{m}$ CMOS process. The thickness of ONO for memory cells is tunnel oxide of 34${\AA}$, nitride of 73${\AA}$ and blocking oxide of 34${\AA}$ . To investigate operating characteristics, CHEI(Channel Hot Electron Injection) method and bit line method are selected as the program and 4he erase operation, respectively. The disturbance characteristics ,according to the program/erase/read cycling are also examined. The degradation characteristics are investigated and then the reliability of SONOS flash memory is guaranteed.

Detection of the Cavity Behind the Tunnel Lining by Single Channel Seismic and GPR Method (GPR 및 단일채널 탄성파탐사에 의한 터널라이닝 배면공동 조사)

  • Shin, Sung-Ryul;Jo, Chul-Hyun;Shin, Chang-Soo;Yang, Seung-Jin;Jang, Won-Yil
    • Journal of the Korea institute for structural maintenance and inspection
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    • v.2 no.4
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    • pp.148-158
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    • 1998
  • Determining the thickness if concrete lining and detecting of the cavity where is located behind tunnel lining plays an important role in the safety diagnosis of tunnel structure and the quality control. In this study, we made use of GPR and seismic method in order to find the cavity or flaw. Although GPR is very useful method in the concrete lining without rebar, it is difficult to detect the cavity in the reinforced concrete lining. We applied mini-seismic method to the reinforced concrete lining. The obtained seismic data was processed by means of seismic section in time domain and image section of power spectrum in frequency domain using Impact-Echo method as well. The proposed method can accurately show the location and depth of the cavity in the reinforced concrete lining.

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Optimum Channel Thickness of Nanowire-FET

  • Go, Hyeong-U;Kim, Jong-Su;Kim, Sin-Geun;Sin, Hyeong-Cheol
    • Proceeding of EDISON Challenge
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    • 2016.03a
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    • pp.277-279
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    • 2016
  • Nanowire-FET은 Gate-All-Around (GAA) 구조로 차세대 반도체 소자 구조로 여겨지고 있다. Nanowire-FET은 채널 두께에 따라 $I_D-V_G$ curve에 매우 중요한 영향을 끼친다. 따라서 본 논문은, Edison 시뮬레이션을 이용하여 Nanowire-FET의 Silicon Thickness에 따른 여러 특성을 비교하여 최적 Silicon Thickness에 대해 연구하였다.

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Characterization of Solution-Processed Oxide Transistor with Embedded Electron Transport Buffer Layer (전자 수송층을 삽입한 용액 공정형 산화물 트랜지스터의 특성 평가)

  • Kim, Han-Sang;Kim, Sung-Jin
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.30 no.8
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    • pp.491-495
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    • 2017
  • We investigated solution-processed indium-zinc oxide (IZO) thin-film transistors (TFTs) by inserting a 2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole (PBD) buffer layer. This buffer layer efficiently tuned the energy level between the semiconducting oxide channel and metal electrode by increasing charge extraction, thereby enhancing the overall device performance: the IZO TFT with embedded PBD layer (thickness: 5 nm; width: $2,000{\mu}m$; length: $200{\mu}m$) exhibited a field-effect mobility of $1.31cm^2V^{-1}s^{-1}$, threshold voltage of 0.12 V, subthreshold swing of $0.87V\;decade^{-1}$, and on/off current ratio of $9.28{\times}10^5$.

A Study on the I-V characteristics of a delta doped short-channel HEMT (단채널 델타도핑 HEMT의 전압-전류 특성에 대한 2차원적 해석)

  • Lee Jung-Ho;Chae Gyoo-Soo;Kim Min-Nyun
    • Proceedings of the KAIS Fall Conference
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    • 2004.06a
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    • pp.158-161
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    • 2004
  • In this study, an analytical model for I-V characteristics of an n-AIGaAs / GaAs Delta doped HEMT is proposed. The two-dimensional electron gas density and the conduction band edge profile are calculated from a self-consistent iterative solution of the Poisson equation. The parameters, which include the saturation velocity, two-dimensional electron gas concentration, thickness of the doped and undoped layer(AIGaAs, GaAs, spacer etc.,), are in good agreement with the independent calculations.

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A Study on the Modeling of Leakage Current in Polysilicon TFT (다결정 실리콘 TFT의 누설전류 모델링에 관한 연구)

  • Park, Jung-Hoon;Lee, Joo-Chang;Kim, Young-Cig;Rhie, Dong-Hee;Sung, Man-Young
    • Proceedings of the KIEE Conference
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    • 1993.07b
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    • pp.1250-1252
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    • 1993
  • Enhancement mode n-channel TFT leakage current(off current : $V_G<0$) that is little agreement on the conduction mechanism is major disadvantage of poly-silicon TFT in practical use, characteristic analysis and model ing. In this paper, new modeling of leakage current is proposed. The activation energy of leakage current, which is dependent on gate voltage, and leakage current dependent on poly silicon thickness are plausibly explained with this model. This model indicate that the reduction of leakage current is attributable to a decrease of maximum laterial electric field strength in the drain depletion region and to the density of trap.

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Study of Mechanics of Remote Sensing and Exploring Method in Layered Medium

  • Ai-lan, LAN;Sheng-wei, ZHANG;Jing-shan, Jiang
    • Proceedings of the KSRS Conference
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    • 2003.11a
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    • pp.1356-1358
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    • 2003
  • In the paper, a method making use of the characteristics of Dyad Green Function (DGF) and Fluctuation-Dissipation Theorem to get the brightness temperature of layered medium is introduced. Based on the approach and the measured data of multi-channel radiometer and Least Square Method (LSM), the thickness of lunar soil can be retrieved. These methods are significant to study on materials on lunar surface.

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Improved sintering process of counter electrode for dye-sensitized solar cells

  • Lee, Su Young;Kim, Sang Ho
    • Proceedings of the Korean Institute of Surface Engineering Conference
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    • 2012.05a
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    • pp.227-228
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    • 2012
  • In interfaces between carbon black or Pt and FTO glass in dye-sensitized solar cell counter electrodes, a marginal resistant channel for electrons, we tried to improve the connection by modifying the sintering process. A stepwise sintering process for carbon black and Pt counter electrodes was applied and its effect on power conversion efficiency was studied. Power conversion efficiencies of built-in DSSC made by a one-step sintering process with carbon black and Pt counter electrodes were about 5.01% and 5.02%, respectively. Cells made with the stepwise sintering process were 5.96% and 6.21%, respectively, indicating an 20% improvement. Fill factor (FF) increased, and it was them main reason for the power conversion efficiency improvement. Step wise sintering increased the adhesion of the interface and reduced the film thickness and surface roughness. As a result, the resistivity of the counter electrode and EIS impedance of DSSCs decreased.

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