• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.497-497
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• 2013

Semiconducting amorphous InGaZnO (a-IGZO) has attracted significant research attention as improved deposition techniques have made it possible to make high-quality a-IGZO thin films. IGZO thin films have several advantages over thin film transistors (TFTs) based on other semiconducting channel layers.The electron mobility in IGZO devices is relatively high, exceeding amorphous Si (a-Si) by a factor of 10 and most organic devices by a factor of $10^2$. Moreover, in contrast to other amorphous semiconductors, highly conducting degenerate states can be obtained with IGZO through doping, yet such a state cannot be produced with a-Si. IGZO thin films are capable of mobilities greaterthan 10 $cm^2$/Vs (higher than a-Si:H), and are transparent at visible wavelengths. For oxide semiconductors, carrier concentrations can be controlled through oxygen vacancy concentration. Hence, adjusting the oxygen partial pressure during deposition and post-deposition processing provides an effective method of controlling oxygen concentration. In this study, we deposited IGZO thinfilms at optimized conditions and then analyzed the film's electrical properties, surface morphology, and crystal structure. Then, we explored how to generate IGZO thin films using DC magnetron sputtering. We also describe the construction and characteristics of a bottom-gate-type TFT, including the output and transfer curves and bias stress instability mechanism.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.82-82
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• 2008

One-dimensional (1D) nanowires have been received much attention due to their potential for applications in various field. Recently some logic applications fabricated on various nanowires, such as ZnO, CdS, Si, are reported. These logic circuits, which consist of two- or three field effect transistors(FETs), are basic components of computation machine such as central process unit (CPU). FETs fabricated on nanowire generally have surrounded shapes of gate structure, which improve the device performance. Highly integrated circuits can also be achieved by fabricating on nano-scaled nanowires. But the numerical and SPICE simulation about the logic circuitry have never been reported and analyses of detailed parameters related to performance, such as channel doping, gate shapes, souce/drain contact and etc., were strongly needed. In our study, NAND and NOT logic circuits were simulated and characterized using 2- and 3-dimensional numerical simulation (SILVACO ATLAS) and built-in spice module(mixed mode).

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.5
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• pp.38-45
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• 1989

We have studied the electrical characteristics of the hydrogenated amorphous silicon (a-Si:H) ambiploar thin film transistors (TET'S)using 100ppm boron-doped a-Si:H as an active layer. The enhancement of drain current due to the double injection behavior has been observed in the p-channel operation of the TFT. The drain current decreases with time in streched exponential form when the gate voltage is positive. The result indicates that the dangling bonds created by electron accumulation show identical time dependence as the diffusion of hydrogen in the film. We observed the experimental evidence that the doping efficiency changes either when the gate bias is applied or when the light is illuminated on boron-doped a-Si:H.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.751-754
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• 2003

Metamorphic HEMTs (MHEMTs) have emerged as excellent challenges for the design and fabrication of high-speed HEMTs for millimeter-wave applications. Some of improvements result from improved mobility and larger conduction band discontinuity in the channel, leading to more efficient modulation doping, better confinement, and better device performance compared with pseudomorphic HEMTs. We have studied the calibration on the DC and RF characteristics of the MHEMT device using I $n_{0.53}$G $a_{0.47}$As/I $n_{0.52}$A1$_{0.48}$As modulation-doped heterostructure on the GaAs wafer. For the optimized device performance simulation, we calibrated the device performance of 0.1-${\mu}{\textrm}{m}$ $\Gamma$-gate MHEMT fabricated in our research center using the 2D ISE-DESSIS device simulator. With this calibrated parameter set, we have obtained very good reproducibility. The device simulation on the DC and RF characteristics exhibits good reproducibility for our 0.1-${\mu}{\textrm}{m}$ -gate MHEMT device compared with the measurements. We expect that our calibration result can help design over-100-GHz MHEMT devices for better device performance.ormance.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.5
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• pp.394-398
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• 2007

A simple doping method to fabricate a very thin channel body of the nano-scaled n-type fin field-effect-transistor (FinFET) by arsenic solid-Phase-diffusion (SPD) process is presented. Using the As-doped spin-on-glass films and the rapid thermal annealing for shallow junction, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. The n-type FinFET devices with a gate length of 20-100 nm were fabricated by As-SPD and revealed superior device scalability.

• Bulletin of the Korean Chemical Society
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• v.24 no.3
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• pp.285-290
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• 2003

An analytical method for the simultaneous determination of trace Ge, As and Se in biological samples by inductively coupled plasma/mass spectrometry has been investigated. The effects of added organic gas into the coolant argon gas on the analyte signal were studied to improve the detection limit, accuracy and precision. The addition of a small amount of methane (10 mL/min.) into the coolant gas channel improved the ionization of Ge, As and Se. The analytical sensitivity of the proposed Ar/CH₄system was superior by at least two-fold to that of the conventional Ar method. In the present method, the detection limits obtained for Ge, As and Se were 0.014, 0.012 and 0.064 ㎍/L, respectively. The analytical reliability of the proposed method was evaluated by analyzing the certified standard reference materials (SRM). Recoveries of 99.9% for Ge, 103% for As, 96.5% for Se were obtained for NIST SRM of freeze dried urine sample. The proposed method was also applied to the biological samples.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.199-199
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• 2008

이 실험은 NVM의 Oxide, Nitride, Oxide nitride층별 blocking, trapping and tunneling 속성에 대해서 밝히고자 한다. gate 전극은 값싸고 전도도가 좋은 알루미늄을 사용한다. 유리기판위에 Silicon nitride층을 20nm로 코팅하고 Silicon dioxide층을 10nm로 코팅한다. 그리고 amorphous Silicon material이 증착된다. Poly Silicon은 Solid Phase Crystallization 방법을 사용하였다. 마지막 공정으로 p-doping은 ion shower에 의한 방법으로 drain과 source 전극을 생성하였다. gate가 biasing 될 때, p-channel은 source와 drain 사이에서 형성된다. Oxide Nitride Oxide nitride (ONO) 층은 각각 12.5nm/20nm/2.3nm의 두께로 만들었다. 전하는 Program process 중에 poly Silicon층에서 Silicon Oxide nitride tunneling층을 통하여 움직이게 된다. 그리고 전하들은 Silicon Nitride층에 머무르게 된다. 그 전하들은 erasing process 중에 trapping 층에서 poly Silicon 층으로 되돌아 간다. Silicon Oxide blocking층은 trapping층으로 전하가 나가는 것을 피하기 위하여 더해진다. 이 논문에서 Programming process와 erasing process의 Id-Vg 특성곡선을 설명한다. Programming process에 positive voltage를 또는 erasing process에 negative voltage를 적용할 때, Id-Vg 특성 곡선은 왼쪽 또는 오른쪽으로 이동한다. 이 실험이 보여준 결과값에 의해서 10년 이상의 저장능력이 있는 메모리를 만들 수 있다. 그러므로, NVM의 중요한 두 가지 성질은 유지성과 내구성이다.

• Journal of the Semiconductor & Display Technology
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• v.10 no.1
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• pp.63-73
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• 2011

Metamorphic HEMTs (MHEMTs) have emerged as excellent challenges for the design and fabrication of high-speed HEMTs for millimeter-wave applications. Some of improvements result from improved mobility and larger conduction band discontinuity in the channel, leading to more efficient modulation doping, better confinement, and better device performance compared with conventional pseudomorphic HEMTs (PHEMTs). For the optimized device design and development, we have performed the calibration on the DC characteristics of our fabricated 0.1 ${\mu}m$ ${\Gamma}$-gate MHEMT device having the modulation-doped $In_{0.52}Al_{0.48}As/In_{0.53}Ga_{0.47}$As heterostructure on the GaAs wafer using the hydrodynamic transport model of a commercial 2D ISE-DESSIS device simulator. The well-calibrated device simulation shows very good agreement with the DC characteristic of the 0.1 ${\mu}m$ ${\Gamma}$-gate MHEMT device. We expect that our calibration result can help design over-100-GHz MHEMT devices for better device performance.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.369-372
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• 2004

The characteristics of antimony implants are relatively well-known. Antimony has lower diffusion coefficient, shorter implantation range, and smaller scattering as compared with conventional dopants such as phosphorous and arsenic. It has been commonly used in the doping of buried layer in Bi-CMOS process. In this paper, characteristics and appropriate condition of monitoring in antimony implant beam tuning using $Sb_2O_3$ were investigated to get a reliable process. TW(Thema Wave) and Rs(Sheet Resistance) test were carried out to set up condition of monitoring for stable operation through the periodic inspection of instruction condition. The monitoring was progressed at the point that the slant of Rs varied significantly to investigate the variation of instruction accurately.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.248-248
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• 2010

CMOS 축소화가 32nm node를 넘어서 지속적으로 진행되기 위하여 FinFET, Surround Gate and Tri-Gate와 같은 Fully Depleted 3-Dimensional 소자들이 SCE를 다루기 위해서 많이 제안되어 왔다. 하지만 소자의 축소화를 진행함에 있어서 좁고 균일한 patterning을 형성하는 것과 동시에 낮은 Extension Region과 Contact Region에서의 Series Resistance을 제공하여야 하고 Source/Drain Contact Formation을 확보하여야 한다. 그리고 소자의 축소화가 진행됨으로써 Silicide의 응집현상과 Source/Drain Junction의 누설전류에 대한 허용범위가 점점 엄격해지고 있다. ITRS 2005에 따르면 32nm CMOS에서는 Contact Resistivity가 대략 $2{\times}10-8{\Omega}cm2$이 요구되고 있다. 또한 Three Dimensional 소자에서는 Fin Corner Effect가 Channel Region뿐만 아니라 S/D Region에서도 중대한 영향을 미치게 된다. 따라서 본 논문에서 제시하는 Novel S/D Contact Formation 기술을 이용하여 Self-Aligned Dual/Single Metal Contact을 이루어Patterning에 대한 문제점 해결과 축소화에 따라 증가하는 Contact Resistivity 문제점을 해결책을 제시하고자 한다. 이를 검증하기3D MOSFET제작하고 본 기술을 적용하고 검증한다. 또한 Normal Doping 구조를 가진3D MOSFET뿐만 아니라 SCE를 해결하기 위해서 대안으로 제시되고 있는 SB-MOSFET을 3D 구조로 제작하고, 이 기술을 적용하여 검증한다. 그리고 Silvaco simulation tool을 이용하여 S/D에 Metal이 Contact을 이루는 구조가 Double type과 Triple type에 따라 Contact Resistivity에 미치는 영향을 미리 확인하였고 이를 실험으로 검증하여 소자의 축소화에 따라 대두되는 문제점들의 해결책을 제시하고자 한다.