• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.149-152
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• 2003

Soruce/drain (or, LDD) formation technology is critical to device reliability especially in the case of short channel LTPS-TFT devices. Ion shower doping with a main ion source of $P_2H_x$ was conducted on ELA Poly-Si. We report the effects of annealing methods on dopant activation and damage recovery in ion-shower doped poly-Si.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.136-147
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• 2005

A theoretical design evaluation based on a hydrodynamic transport simulation of strained Si-SiGe on insulator (SSOI) type nMOSFETs is reported. Although, the net performance improvement is quite limited by the short channel effects, simulation results clearly show that the strained Si-SiGe type nMOSFETs are well-suited for gate lengths down to 20 nm. Simulation results show that the improvement in the transconductance with decreasing gate length is limited by the long-range Coulomb scattering. An influence of lateral and vertical diffusion of shallow dopants in the source/drain extension regions on the device performance (i.e., threshold voltage shift, subthreshold slope, current drivability and transconductance) is quantitatively assessed. An optimum layer thickness ($t_{si}$ of 5 and $t_{sg}$ of 10 nm) with shallow Junction depth (5-10 nm) and controlled lateral diffusion with steep doping gradient is needed to realize the sub-50 nm gate strained Si-SiGe type nMOSFETs.

• Journal of IKEEE
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• v.22 no.3
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• pp.565-569
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• 2018

For the conventional power MOSFET (metal-oxide semiconductor field-effect transistor) device structure, there exists a tradeoff relationship between specific on-state resistance (Ron,sp) and breakdown voltage (BV). In order to overcome this tradeoff, a super-junction (SJ) trench MOSFET (TMOSFET) structure with uniform or non-uniform doping concentration, which decreases linearly in the vertical direction from the N drift region at the bottom to the channel at the top, for an optimal design is suggested in this paper. The on-state resistance of $0.96m{\Omega}-cm2$ at the SJ TMOSFET is much less than that at the conventional power MOSFET under the same breakdown voltage of 100V. A design methodology for the edge termination is proposed to achieve the same breakdown voltage and on-state resistance as the main body of the super-junction TMOSFET by using of the SILVACO TCAD 2D device simulator, Atlas.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.11a
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• pp.14-17
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• 1992

To analyze Nonvolatile SNOSFET(polySilicon-Nitride-Oxide-Semiconductor Field Effect Transistor) memory device, two dimensional numerical computer simulation program was developed. The equation discretization was performed by the Finite difference method and the solution was derived by the Iteration method. The doping profile of n-channel device which was fabricated by 1Mbit CMOS process was observed. The electrical potential and the carrier concentration distribution to applied bias condition were observed in the inner of a device. As a result of the write and the erase to memory charge quantity, the threshold voltage shift is expected. Therefore, without device fabrication, the operating characteristics of the device was observed under various the processing and the operating condition.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.4
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• pp.40-50
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• 1993

In this paper, MODFET devices with various gate length are simulated using the Monte-Carlo method. The number of superparticle is 5000 and the Poisson equation is solved to obtain field distribution. The structure of MODFET is n-AlGaAs/i-AlGaAs/iGaAs and doping concentration of n-AlGaAs layer is 1${\times}10^{17}/cm^{3}$ and the thickness is 500.angs., and the thickness of i-AlGaAs is 50$\AA$. The devices with gate length 0.2$\mu$m, 0.5$\mu$m, 1.0$\mu$m respctively are simulated and the current-voltage curves and transport characteristics of that devices are obtained. Occupancy of each subband and electron energy distribution and conduction energy band in channel have been analyzed to obtain transport characteristics, and particles transposed from source to drain have been analyzed to current-voltage curves. Current level is highest for the device of Lg=0.2$\mu$m and transconductance of this device is 310mS/mm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.858-860
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• 2015

본 연구에서는 비대칭 이중게이트 MOSFET의 채널 내 도핑농도에 대한 드레인 유도 장벽 감소 현상에 대하여 분석하고자한다. 드레인 유도 장벽 감소 현상은 드레인 전압에 의하여 소스 측 전위장벽이 낮아지는 효과로서 중요한 단채널 효과이다. 이를 분석하기 위하여 포아송방정식을 이용하여 해석학적 전위분포를 구하였으며 전위분포에 영향을 미치는 채널도핑 농도뿐만이 아니라 상하단 산화막 두께, 하단 게이트 전압 등에 대하여 드레인 유도 장벽 감소 현상을 관찰하였다. 결과적으로 드레인 유도 장벽 감소 현상은 채널도핑 농도에 따라 큰 변화를 나타냈다. 단채널 효과 때문에 채널길이가 짧아지면 도핑농도에 따른 영향이 증가하였다. 도핑농도에 대한 드레인유도장벽감소 현상의 변화는 상하단 산화막 두께에 따라 큰 변화를 보였으며 산화막 두께가 증가할수록 도핑농도에 따른 변화가 증가하는 것을 알 수 있었다. 또한 하단게이트 전압은 그 크기에 따라 도핑농도의 영향이 변화하고 있다는 것을 알 수 있었다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.863-865
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• 2015

본 연구에서는 비대칭 이중게이트 MOSFET의 채널 내 도핑농도분포에 대한 드레인유도장벽감소(Drain Induced Barrier Lowering; DIBL)에 대하여 분석하고자한다. DIBL은 드레인 전압에 의하여 소스 측 전위장벽이 낮아지는 효과로서 중요한 단채널 효과이다. 이를 분석하기 위하여 포아송방정식을 이용하여 해석학적 전위분포를 구하였으며 전위분포에 영향을 미치는 채널도핑농도의 분포함수변화에 대하여 DIBL을 관찰하였다. 채널길이, 채널두께, 상하단 게이트 산화막 두께, 하단 게이트 전압 등을 파라미터로 하여 DIBL을 관찰하였다. 결과적으로 DIBL은 채널도핑농도분포함수의 변수인 이온주입범위 및 분포편차에 변화를 나타냈다. 특히 두 변수에 대한 DIBL의 변화는 최대채널도핑농도가 $10^{18}/cm^3$ 정도로 고도핑 되었을 경우 더욱 현저히 나타나고 있었다. 채널길이가 감소할수록 그리고 채널두께가 증가할수록 DIBL은 증가하였으며 하단 게이트 전압과 상하단 게이트 산화막 두께가 증가할수록 DIBL은 증가하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.12
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• pp.759-763
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• 2016

We demonstrate the utilization of ion gel gate dielectrics for operating non-volatile transistor memory devices based on polymer semiconductor thin films. The gating process in typical electrolyte-gated polymer transistors occurs upon the penetration and escape of ionic components into the active channel layer, which dopes and dedopes the polymer film, respectively. Therefore, by controlling doping and dedoping processes, electrical current signals through the polymer film can be memorized and erased over a period of time, which constitutes the transistor-type memory devices. It was found that increasing the thickness of polymer films can enhance the memory performance of device including (i) the current signal ratio between its memorized state and erased state and (ii) the retention time of the signal.

• Transactions on Electrical and Electronic Materials
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• v.7 no.4
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• pp.173-179
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• 2006

Due to the limitations of the channel length, the lateral spread for two-dimensional impurity distributions is critical for the analysis of devices including the integrated complementary metal oxide semiconductor (CMOS) circuits and high frequency semiconductor devices. The developed codes were then compared with the two-dimensional implanted profiles measured by transmission electron microscope (TEM) as well as simulated by a commercial TSUPREM4 for verification purposes. The measured two-dimensional TEM data obtained by chemical etching-method was consistent with the results of the developed analytical model, and it seemed to be more accurate than the results attained by a commercial TSUPREM4. The developed codes can be applied on a wider energy range $(1KeV{\sim}30MeV)$ than a commercial TSUPREM4 of which the maximum energy range cannot exceed 1MeV for the limited doping elements. Moreover, it is not only limited to diffusion process but also can be applied to implantation due to the sloped and nano scale structure of the mask.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.9
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• pp.397-407
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• 2002

A new simulator which predicts the quantum effect in NMOSFET structure is developed. Using the self-consistent method by numerical method, this simulator accurately predicts the carrier distribution due to improved calculation precision of potential in the inversion layer. However, previous simulator uses analytical potential distribution or analytic function based fitting parameter Using the developed simulator, threshold voltage increment and gate capacitance reduction due to the quantum effect are analyzed in NMOS. Especially, as oxide thickness and channel doping dependence of quantum effect is analyzed, and the property analysis for the next generation device is carried out.