• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.6 s.324
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• pp.1-7
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• 2004

The development of direct receiver techniques is expected to be a solution for future wideband or multi-band wireless systems based on software defined radio. In this Paper, we study the regeneration of I and Q signals for the SDR based direct conversion receiver, so that we can handle a wide bandwidth and maintain maximal flexibility in system utilization. After modeling the basic system considering the real wireless communication environment, and studying the impact of imperfect phase imbalance on the performance of a direct conversion receiver, we propose a suboptimal I and Q signal regeneration algorithm for the system. The proposed algerian regenerates I and Q signals using a real time early-late compensator which effectively estimates phase imbalances and gives feedback in a directreceiver. The proposed algorithm is shown to mitigate the impact of AWGN and improves performance especially at low SNR channel condition. According to the computer simulation, the BER performance of the proposed system is at least about 4 dB better than conventional systems under $45{\~}55$ degrees random phase errors.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.1
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• pp.7-13
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• 1998

The VLSI devices of submicron level trend to have a lowering of reliability because of hot carriers by two dimensional influences which are caused by short channel effects and which are not generated in a long channel devices. In order to minimize the two dimensional influences, much research has been made into various types of source/drain structures. MOS typed tunnel transistor with Schottky barrier junctions at source/drain, which has the advantages in fabrication process, downsizing and response speed, has been proposed. The experimental device was fabricated with p type silicon, and manifested the transistor action, showing the unsaturated output characteristics and the high transconductance comparing with that in field effect mode. The results of trial indicate for better performance as follows; high doped channel layer to lower the driving voltage, high resistivity substrate to reduce the leakage current from the substrate to drain.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.3
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• pp.161-164
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• 2000

A simple methode for calculating the forward voltage drop of IGBTs is presented, on the voltage drops on the p+ body, the reverse biased depletion region between p+body and epi-layer, the epi layer, and the forward biased collector junction. The decrease of the total current density in the epi layer near the p+ body is taken into account. The proposed methode allows a simple but accurate determination of the forward voltage drop in IGBTs, avoiding the complex path taken in the previous model for the forward voltage drops on channel, accumulation region, and epi region. Numerical simulations for 1kV NPT-IGBT with a uniformly doped collector are shown to support the analytical results.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.455-459
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• 2004

Electrostatic discharge(ESD) is a serious reliability concern. It causes approximately most of all field failures of integrated circuits. Inevitably, future IC technologies will shrink the dimensions of interconnects, gate oxides, and junction depths, causing ICs to be increasingly susceptible to ESD-induced damage [1][2][3]. This thesis shows the optimization of the ESD protection circuit based on the tested results of MM (Machine Model) and HBM (Human Body Model), regardless of existing Reference in fully silicided 0.18 um CMOS process. His thesis found that, by the formation of silicide in a source and drain contact, the dimensions around the contact had a less influence on the ESD robustness and the channel width had a large influence on the ESD robustness [8].

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.1258-1261
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• 2004

Degradation phenomenon in the low-temperature polysilicon (LTPS) thin-film transistors (TFTs) with different junction structures was investigated. A gate-overlapped lightly doped drain (GOLDD) structure showed better hot-carrier stress (HCS) stability than a conventional LDD one. On the other hand, high drain current stress (HDCS) at $V_{gs}$ = $V_{ds}$ conditions caused much severe device degradation in the GOLDD structure because of its higher current level resulting in the higher applied power. It is suggested that self-heating-induced mobility degradation in the GOLDD TFFs be suppressed for using this structure in short-channel devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.10
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• pp.894-900
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• 2006

This paper reports the fabrication and characterization of $32{\times}32$ thermal cantilever array for nano-scaled memory device applications. The $32{\times}32$ thermal cantilever array with integrated tip heater has been fabricated with micro-electro-mechanical systems(MEMS) technology on silicon on insulator(SOI) wafer using 9 photo masking steps. All of single-level cantilevers(1,024 bits) have a p-n junction diode in order to eliminate any electrical cross-talk between adjacent cantilevers. Nonlinear electrical characteristic of fabricated thermal cantilever shows its own thermal heating mechanism. In addition, n-channel high-voltage MOSFET device is integrated on a wafer for embedding driver circuitry.

• Proceedings of the Korean Society of Agricultural Engineers Conference
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• 2002.10a
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• pp.453-456
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• 2002

In this study, the effect of DEM resolution (15m, 30m, 50m, 70m, 100m, 200m, 300m) on the hydrological simulation was examined using BASINS (Better Assessment Science Integrating point and Nonpoint Source) for Heukcheon watershed (303.3km2) data from 1998 to 1999. Generally, as the cell size of DEM increased, topographical changes were observed as the original range of elevation decreased. The processing time of watershed delineation and river network needed more time and effort on smaller cell size of DEM. The larger DEM demonstrated had some errors in the junction of river network which might effects on the simulation of water quantity and quality. The area weighted average watershed slope became lower but the length weighted average channel slope became higher as the DEM size increased. DEM resolution affected substantially on the topographical parameter but less on the hydrological simulation. Considering processing time and accuracy on hydrological simulation DEM mesh size of 100m is recommended for this watershed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.104-109
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• 2008

A simple and efficient way of modeling backgating in GaAs MESFET's is presented through depletion width modulation of Schottky junction and channel-substrate interface. It is shown semi-empirically that such a modulation of depletion widths causes serious troubles in designing precision circuits since backgating drastically reduces threshold voltage of MESFET as well as drain current. Finally, some of the results are compared with reported experimental results. This model may serve as a starting point for rigorous characterization of backgating effect on various device parameters of GaAs MESFET's.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.136-147
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• 2005

A theoretical design evaluation based on a hydrodynamic transport simulation of strained Si-SiGe on insulator (SSOI) type nMOSFETs is reported. Although, the net performance improvement is quite limited by the short channel effects, simulation results clearly show that the strained Si-SiGe type nMOSFETs are well-suited for gate lengths down to 20 nm. Simulation results show that the improvement in the transconductance with decreasing gate length is limited by the long-range Coulomb scattering. An influence of lateral and vertical diffusion of shallow dopants in the source/drain extension regions on the device performance (i.e., threshold voltage shift, subthreshold slope, current drivability and transconductance) is quantitatively assessed. An optimum layer thickness ($t_{si}$ of 5 and $t_{sg}$ of 10 nm) with shallow Junction depth (5-10 nm) and controlled lateral diffusion with steep doping gradient is needed to realize the sub-50 nm gate strained Si-SiGe type nMOSFETs.

• 한국가시화정보학회:학술대회논문집
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• 2003.11a
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• pp.87-90
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• 2003

In this paper, flow characteristics of plasma flow in a micro-tube were investigated experimentally using Micro-PIV. For comparision, the experiments were repeated for DI-water instead of plasma. Both velocity profiles of Plasma and DI-water are well agreed with the theoretical velocity distribution of newtonian fluid. We also carried out generating plasma-in-oil droplet formation at a Y-junction microchannel. In order to clarify the hydrodynamic aspects involved in plasma droplet formation. Rhodamin B were mixed with plasma only for visualization of plasma droplet.