• The Korean Journal of Physiology and Pharmacology
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• v.16 no.1
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• pp.25-30
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• 2012

Under some pathological conditions as bile flow obstruction or liver diseases with the enterohepatic circulation being disrupted, regurgitation of bile acids into the systemic circulation occurs and the plasma level of bile acids increases. Bile acids in circulation may affect the nervous system. We examined this possibility by studying the effects of bile acids on gating of neuronal (N)-type $Ca^{2+}$ channel that is essential for neurotransmitter release at synapses of the peripheral and central nervous system. N-type $Ca^{2+}$ channel currents were recorded from bullfrog sympathetic neuron under a cell-attached mode using 100 mM $Ba^{2+}$ as a charge carrier. Cholic acid (CA, $10^{-6}M$) that is relatively hydrophilic thus less cytotoxic was included in the pipette solution. CA suppressed the open probability of N-type $Ca^{2+}$ channel, which appeared to be due to an increase in (no activity) sweeps. For example, the proportion of sweep in the presence of CA was ~40% at +40 mV as compared with ~8% in the control recorded without CA. Other single channel properties including slope conductance, single channel current amplitude, open and shut times were not significantly affected by CA being present. The results suggest that CA could modulate N-type $Ca^{2+}$ channel gating at a concentration as low as $10^{-6}M$. Bile acids have been shown to activate nonselective cation conductance and depolarize the cell membrane. Under pathological conditions with increased circulating bile acids, CA suppression of N-type $Ca^{2+}$ channel function may be beneficial against overexcitation of the synapses.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.115-120
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• 2008

Carrier velocity in the MOSFET channel is the main driving force for improved transistor performance with scaling. We report measurements of the drift velocity of electrons and holes in silicon inversion layers. A technique for extracting effective carrier velocity which is a more accurate extraction method based on the actual inversion charge measurement is used. This method gives more accurate result over the whole range of $V_{ds}$, because it does not assume a linear approximation to obtain the inversion charge and it does not limit the range of applicable $V_{ds}$. For a very short channel length device, the electron velocity overshoot is observed at room temperature in 37 nm MOSFETs while no hole velocity overshoot is observed down to 36 nm. The electron velocity of short channel device was found to be strongly dependent on the longitudinal field.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1268-1270
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• 1993

In this study, the characteristics of Si-$SiO_2$ interface and its degradation in short channel SONOSFET nonvolatile memory devices, fabricated by 1Mbit CMOS process($1.2{\mu}m$ design rule), with $65{\AA}$ blocking oxide layer, $205{\AA}$ nitride layer, and $30{\AA}$ tunneling oxide layer on the silicon wafer were investigated using the charge pumping method. For investigating the Si-$SiO_2$ interface characteristics before and after write/erase cycling, charge pumping current characteristics with frequencies, write/erase cycles, as a parameters, were measured. As a result, average Si-$SiO_2$ interface trap density and mean value of capture cross section were determined to be $1.203{\times}10^{11}cm^{-2}eV^{-1}\;and\;2.091{\times}10^{16}cm^2$ before write/erase cycling, respectively. After cycling, when the write/erase cycles are $10^4$, average $Si-SiO_2$ interface trap density was $1.901{\times}10^{11}cm^{-2}eV^{-1}$. Incresing write/erase cycles beyond about $10^4$, Si-$SiO_2$ interface characteristics with write/erase cycles was increased logarithmically.

• Journal of IKEEE
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• v.25 no.4
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• pp.774-777
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• 2021

In this paper, we analyzed the gate controllability of 3D NAND Flash Memory with Charge Trap Flash using Ferroelectric (CTF-F) structure. HfO₂, a ferroelectric material, has a high-k characteristic besides polarization. Due to these characteristics, gate controllability is increased in CTF-F structure and on/off current characteristics are improved in Bit Line(BL). As a result of the simulation, in the CTF-F structure, the channel length of String Select Line(SSL) and Ground Select Line(GSL) was 100 nm, which was reduced by 33% compared to the conventional CTF structure, but almost the same off-current characteristics were confirmed. In addition, it was confirmed that the inversion layer was formed stronger in the channel during the program operation, and the current through the BL was increased by about 2 times.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.10
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• pp.1-7
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• 2020

In recent years, as LED display systems are actively spread, study on effective control methods for an LED driver for driving the systems has been in progress. The most representative among them is the uniform brightness control method for the LED driver channel. In this paper, we propose an LED driver IC for BLU with current compensation and system protection functions to minimize channel luminance deviation. It is designed for current accuracy within ±3% between channels and a channel current of 150 mA. In order to satisfy the design specifications, the channel amplifier offset was canceled out by a chopping operation using a channel-driving PWM signal. Also, a pre-charge function was implemented to minimize the fast operation speed and luminance deviation between channels. LED error (open, short), switch TR short detection, and operating temperature protection circuits were designed to protect the IC and BLU systems. The proposed IC was fabricated using a Magnachip 0.35-um CMOS process and verified using Cadence and Synopsys' Design Tool. The fabricated LED driver IC has current accuracy within ±1.5% between channels and 150-mA channel output characteristics. The error detection circuits were verified by a test board.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.434.2-434.2
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• 2014

We observe enhanced pH response of solution-gated field-effect transistors (SG-FET) having 1D-2D hybrid channel of vertical grown ZnO nanorods grown on CVD graphene (Gr). In recent years, SG-FET based on Gr has received a lot of attention for biochemical sensing applications, because Gr has outstanding properties such as high sensitivity, low detection limit, label-free electrical detection, and so on. However, low-defect CVD Gr has hardly pH responsive due to lack of hydroxyl group on Gr surface. On the other hand, ZnO, consists of stable wurtzite structure, has attracted much interest due to its unique properties and wide range of applications in optoelectronics, biosensors, medical sciences, etc. Especially, ZnO were easily grown as vertical nanorods by hydrothermal method and ZnO nanostructures have higher sensitivity to environments than planar structures due to plentiful hydroxyl group on their surface. We prepared for ZnO nanorods vertically grown on CVD Gr (ZnO nanorods/Gr hybrid channel) and to fabricate SG-FET subsequently. We have analyzed hybrid channel FETs showing transfer characteristics similar to that of pristine Gr FETs and charge neutrality point (CNP) shifts along proton concentration in solution, which can determine pH level of solution. Hybrid channel SG-FET sensors led to increase in pH sensitivity up to 500%, compared to pristine Gr SG-FET sensors. We confirmed plentiful hydroxyl groups on ZnO nanorod surface interact with protons in solution, which causes shifts of CNP. The morphology and electrical characteristics of hybrid channel SG-FET were characterized by FE-SEM and semiconductor parameter analyzer, respectively. Sensitivity and sensing mechanism of ZnO nanorods/Gr hybrid channel FET will be discussed in detail.

• Journal of Korea Society of Digital Industry and Information Management
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• v.11 no.3
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• pp.91-98
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• 2015

There is a new evolution in technological advancement taking place called the Internet of Things (IoT), The IoT enables physical world objects in our surrounding to be connected to the Internet. ISM (Industrial Scientific Medical) band that is 2.4GHz band authorized free of charge is being widely used for smart devices. Accordingly studies have been continuously conducted on the possibility of coexistence among nodes using ISM band. In particular, the interference of IEEE 802.11b based Wi-Fi devices using overlapping channel during communication among IEEE 802.15.4 based wireless sensor nodes suitable for low-power, low-speed communication using ISM band. Because serious network performance deterioration of wireless sensor networks. In this paper, we will propose an algorithm that identifies the possibility of using more accurate channels by mixing utilization of interference signal and RSSI (Received Signal Strength Indicator) Min/Max/Activity of Interference signal by wireless sensor nodes. In addition, it will verify our algorithm by using OPNET Network verification simulator.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.41-44
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• 2004

The trend of decreasing the minimal structure sizes in microelectronics is still being continued. Therefore in its roadmap the Semiconductor Industries Association predicts a printed minimum MOS-transistor channel length of 10 nm for the year 2018. Although the resolution of optical lithography still dramatically increases, there are known and proved solutions for structure sizes significantly below 50 nm up to now. In this work a new method for the fabrication of extremely small MOS-transistors with a channel length and width below 50 nm with low demands to the used lithography will be explained. It's a further development of our deposition and etchback technique which was used in earlier research to produce transistors with very small channel lengths down to 30 nm, with a scaling of the transistor's width. The used technique is proved in a first charge of MOS-transistors with a channel area of W=200 nm and L=80 nm. The full CMOS compatible technique is easily transferable to almost any other technology line and results in an excellent homogeneity and reproducibility of the generated structure size. The electrical characteristics of such small transistor will be analyzed and the ultimate limits of the technique will be discussed.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.5
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• pp.67-78
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• 1984

EAROM device is an n-channel MOS transistor with a control gate stack ed on the floating gate. On account of channel injection type, channel lengths are designed 4-8 $\mu$m and chinnel widths 5-14 $\mu$m. These devices which have fourstructures of different type control gate are designed by NMOS 5 $\mu$m design rule and fabricated by double polysilicon gate NMOS Process. Double ion implantation is applied to increase punchthrough voltage and gate-controlled channel breakdown voltage. The drain and gate voltage for programming was 13-17V and 20-25V, respectively. EPROM cell fabricated could be erased not by optical method but by electrical method. The result of charge retention test showed decrease in stored charges by 4% after 200 hours at 1$25^{\circ}C$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.20-20
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• 2007

Nanowire-based field-effect transistors (FETs) decorated with nanoparticles have been greatly paid attention as nonvolatile memory devices of next generation due to their excellent transportation ability of charge carriers in the channel and outstanding capability of charge trapping in the floating gate. In this work, top-gate single ZnO nanowire-based FETs with and without Au nanoparticles were fabricated and their memory effects were characterized. Using thermal evaporation and rapid thermal annealing processes, Au nanoparticles were formed on an $Al_2O_3$ layer which was semi cylindrically coated on a single ZnO nanowire. The family of $I_{DS}-V_{GS}$ curves for the double sweep of the gate voltage at $V_{DS}$ = 1 V was obtained. The device decorated with nanoparticles shows giant hysterisis loops with ${\Delta}V_{th}$ = 2 V, indicating a significant charge storage effect. Note that the hysterisis loops are clockwise which result from the tunneling of the charge carriers from the nanowire into the nanoparticles. On the other hand, the device without nanoparticles shows a negligible countclockwise hysterisis loop which reveals that the influence of oxide trap charges or mobile ions is negligible. Therefore, the charge storage effect mainly comes from the nanoparticles decorated on the nanowire, which obviously demonstrates that the top-gate single ZnO nanowire-based FETs decorated with Au nanoparticles are the good candidate for the application in the nonvolatile memory devices of next generation.