• ETRI Journal
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• v.24 no.5
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• pp.333-340
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• 2002

We propose a new process technique for fabricating very high-density trench MOSFETs using 3 mask layers with oxide spacers and a self-aligned technique. This technique reduces the device size in trench width, source, and p-body region with a resulting increase in cell density and current driving capability as well as cost-effective production capability. We were able to obtain a higher breakdown voltage with uniform oxide grown along the trench surface. The channel density of the trench DMOSFET with a cell pitch of 2.3-2.4 ${\mu}m$ was 100 Mcell/$in^2$ and a specific on-resistance of 0.41 $m{\Omega}{\cdot}cm^2$ was obtained under a blocking voltage of 43 V.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.310-311
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• 2011

Dual-frequency (DF) capacitively coupled plasmas (CCP) are used to separately control the mean ion energy and flux at the electrodes [1]. This separate control in capacitively coupled radio frequency discharges is one of the most important issues for various applications of plasma processing. For instance, in the Plasma Enhanced Chemical Vapor Deposition processes such as used for solar cell manufacturing, this separate control is most relevant. It principally allows to increase the ion flux for high deposition rates, while the mean ion energy is kept constant at low values to prevent highly energetic ion bombardment of the substrate to avoid unwanted damage of the surface structure. DF CCP can be analyzed in a fashion similar to single-frequency (SF) driven with effective parameters [2]. It means that DF CCP can be converted into SF CCP with effective parameters such as effective frequency and effective current density. In this study, comparison of DF CCP and its converted effective SF CCP is carried out through particle-in-cell/Monte Carlo (PIC-MCC) simulations. The PIC-MCC simulation shows that DF CCP and its converted effective SF CCP have almost the same plasma characteristics. In DF CCP, the negative resistance arises from the competition of the effective current and the effective frequency [2]. As the high-frequency current increases, the square of the effective frequency increases more than the effective current does. As a result, the effective voltage decreases with the effective current and it leads to an increase of the ion flux and a decrease of the mean ion energy. Because of that, the negative resistance regime can be called the preferable regime for solar cell manufacturing. In this preferable regime, comparison of DF (13.56+100 or 200 MHz) CCP and SF (60 MHz) CCP with the same effective current density is carried out. At the lower effective current density (or at the lower plasma density), the mean ion energy of SF CCP is lower than that of DF CCP. At the higher effective current density (or at the higher plasma density), however, the mean ion energy is lower than that of SF CCP. In this case, using DF CCP is better than SF CCP for solar cell manufacturing processes.

• Biotechnology and Bioprocess Engineering:BBE
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• v.5 no.2
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• pp.106-109
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• 2000

Vascular endothelial cells (EGs) are usually difficult to culture to culture in a large scale because of their complicated requirements for cell growth. As the vascular endothelial growth factor (VEGF) is a key growth factor in the EC culture, we transfected human umbilical vein endothelial cells (HUVEC) using a plasmid containing VEGF gene and let them grow in a culture medium eliminated an important supplement, endothelail cell growth supplement(ECGS). The expression of VEGF by HUVEC tansfected with Vegf GENE was not enough to stimulate the growth of HUVEC, only 40% of maximum cell density obtainable in the presence of ECGS. However, when the culture medium was supplied with 2.5 ng/ml of basic fibroblast growth factor (bFGF), a synergistic effect effect of VEGE and bFGF was observed. In this case, the final cell density was recovered was recovered up to about 78% of maxium value.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.222-227
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• 2004

The sub-bitline (SBL) sensing voltage of a cell and total cell array can be measured by the method of SBL voltage evaluation method. The MOSAID tester can collect all SBL signals. The hierarchical bitline of unit cell array block is composed of the cell array of 2k rows and 128 columns, which is divided into 32 cell array sections. The unit cell array section is composed of the cell array of 64 rows and 128 columns. The average sensing voltage with 2Pr value of $5{\mu}C/cm^2$ and SBL capacitance of 40fF is about 700mV at 3.0V operation voltage. That is high compensation method for capacitor size degradation effect. Thus allowed minimum 2Pr value for high density Ferroelectric RAM (FeRAM) can move down to about less than $5{\mu}C/cm^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.11-20
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• 2008

The structure of 2-bit/cell flash memory device was characterized for sub-50 nm non-volatile memory (NVM) technology. The memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region, and is erased (or programmed) by using band-to-band tunneling hot-hole injection (or channel hot-electron injection). It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the $V_{th}$ margin for 2-bit/cell operation by ${\sim}2.5$ times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the $V_{th}$ margin more than ${\sim}1.5V$. For a bit-programmed cell, reasonable bit-erasing characteristics were shown with the bias and stress pulse time condition for 2-bit/cell operation. The length effect of the spacer-type storage node is also characterized. Device which has the charge storage length of 40 nm shown better ${\Delta}V_{th}$ and $V_{th}$ margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ${\sim}10nm$ below the source/drain junction.

• ETRI Journal
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• v.26 no.6
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• pp.520-534
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• 2004

As the density of memories increases, unwanted interference between cells and the coupling noise between bit-lines become significant, requiring parallel testing. Testing high-density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built-in self-test (BIST) algorithm for neighborhood pattern-sensitive faults (NPSFs) and new neighborhood bit-line sensitive faults (NBLSFs). Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a four-cell layout is utilized. This four-cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present algorithm properties such as the capability to detect stuck-at faults, transition faults, conventional pattern-sensitive faults, and neighborhood bit-line sensitive faults.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.423-423
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• 2012

Recently, many researchers made progress in various studies improving the efficiency of dye-sensitized solar cell. In this paper, we used glass textured by wet-chemical etching process for improvement of photocurrent density in dye-sensitized solar cells. This is owing to increase coefficient of light utilization. Consequently, DSSC using the textured glass exhibit a Jsc of 9.49 mA/$cm^2$, a Voc of 0.73 V and a fill factor (FF) of 0.67 with an overall conversion efficiency of 4.64. This result showed increasing of 20% current density and 16% conversion efficiency using the textured glass. These results suggested that glass texturing was very effective in controlling the light-scattering properties into the photovoltaic cell.

• 한국신재생에너지학회:학술대회논문집
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• 2008.05a
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• pp.1-4
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• 2008

Fuel cells have the potential of providing several times higher energy storage densities than those possible using current state-of-the-art lithium-ion batteries, but current energy density of fuel cell system is not better than that of lithium-ion batteries. To achieve the high energy density, volume and weight of fuel cell system need to be reduced by miniaturizing system components such as stack, fuel tank, and balance-of-plant. In this paper, the thin flexible PCB (Printed circuit board) is used as a current collector to reduce the stack volume. Two end plates are made from light weight aluminum alloy plate. The plate surface is wholly oxidized through the anodizing treatment for electrical insulation. The opening rate of cathode plate hole is optimized through unit cell performance measurement of various opening rates. The performances are measured at room temperature and ambient pressure condition without any repulsive air supply. The active area of MEA is 10.08 $cm^2$ and active area per a unit cell is 1.68 $cm^2$. The peak power density is about 210 mW/$cm^2$ and the air-breathing planar stack of 2 Wis achieved as a small volume of 18 cc.

• Journal of Korean Society of Water and Wastewater
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• v.19 no.5
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• pp.632-638
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• 2005

Membrane fouling index such as Silt Density Index (SDI) and Modified Fouling Index (MFI) is an important parameter in design of the integrated RO/NF membrane processes for drinking water treatment. In this study, the effect of particle, membrane and feed water characteristics on membrane fouling index were investigated systematically. Higher fouling index values were observed when filtering suspensions with smaller particle size and higher feed particle concentration. Larger membrane resistance due to smaller pore size resulted in an increased membrane fouling index. The variations of feed water hardness and TDS concentrations did not show any impact on fouling index, suggesting that there were no significant colloidal interactions among particles and thus the porosity of particle cake layer accumulated on the membrane surface could be assumed to be 0.36 according to random packing density. Based on the experimental observations, fundamental membrane fouling index model was developed using Happel Cell. The effect of primary model parameters including particle size ($a_p$), particle concentration ($C_o$), membrane resistance ($R_m$), were accurately assessed without any fitting parameters, and the prediction of membrane fouling index such as MFI exhibited very good agreement with the experimental results.

• Journal of the Korean Ceramic Society
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• v.43 no.9 s.292
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• pp.552-557
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• 2006

A low temperature processing route for fabricating porous SiC ceramics by carbothermal reduction has been demonstrated. Effects of expandable microsphere content, sintering temperature, filler content, and carbon source on microstructure, porosity, compressive strength, cell size, and cell density were investigated in the processing of porous silicon carbide ceramics using expandable microspheres as a pore former. A higher microsphere content led to a higher porosity and a higher cell density. A higher sintering temperature resulted in a decreased porosity because of an enhanced densification. The addition of inert filler increased the porosity, but decreased the cell density. The compressive strength of the porous ceramics decreased with increasing the porosity. Typical compressive strength of porous SiC ceramics with ${\sim}70%$ porosity was ${\sim}13 MPa$.