• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.1
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• pp.183-190
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• 2010

We propose an eFuse one-time programmable (OTP) memory cell based on a logic process, which is programmable by an external program voltage. For the conventional eFuse OTP memory cell, a program datum is provided with the SL (Source Line) connected to the anode of the eFuse going through a voltage drop of the SL driving circuit. In contrast, the gate of the NMOS program transistor is provided with a program datum and the anode of the eFuse with an external program voltage (FSOURCE) of 3.8V without any voltage drop for the newly proposed eFuse cell. The FSOURCE voltage of the proposed cell keeps either 0V or the floating state at read mode. We propose a clamp circuit for being biased to 0V when the voltage of FSOURCE is in the floating state. In addition, we propose a VPP switching circuit switching between the logic VDD (=1.8V) and the FSOURCE voltage. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's $0.15{\mu}m$ generic process is $359.92{\times}90.98{\mu}m^2$.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.168-175
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• 2017

In this paper, a 5V small-area NMOS-diode eFuse OTP memory cell is proposed. This cell which is used in PMICs consists of a 5V NMOS transistor and an eFuse link as a memory part, based on a BCD process. Also, a regulated voltage of V2V ($=2.0V{\pm}10%$) instead of the conventional VDD is used to the pull-up loads of a VREF circuit and a BL S/A circuit to obtain a wider operational voltage range of the eFuse memory cell. When this proposed cells are used in the simulation, their sensing resistances are found to be $15.9k{\Omega}$ and $32.9k{\Omega}$, in the normal read mode and in the program-verify-read mode, respectively. Furthermore, the read current flowing through a non-blown eFuse is restricted to $97.7{\mu}A$. Thus, the eFuse link of a non-blown eFuse OTP memory cell is kept non-blown. The layout area of the designed 1kb eFuse OTP memory IP based on Dongbu HiTek's BCD process is $168.39{\mu}m{\times}479.45{\mu}m(=0.08mm^2)$.

• Bulletin of the Korean Chemical Society
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• v.33 no.9
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• pp.3061-3070
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• 2012

Novel 2-hexylthieno[3,2-b]thiophene-containing conjugated molecules have been synthesized via a reduction reaction using tin chloride in an acidic medium. They exhibited good solubility in common organic solvents and good self-film and crystal-forming properties. The single-crystalline objects were fabricated by a solvent slow diffusion process and then were employed for fabricating field-effect transistors (FETs) along with thinfilm transistors (TFTs). TFTs made of 5 and 6 exhibited carrier mobility as high as 0.10-0.15 $cm^2V^{-1}s^{-1}$. The single-crystal-based FET made of 6 showed 0.70 $cm^2V^{-1}s^{-1}$ which was relatively higher than that of the 5-based FET (${\mu}=0.23cm^2V^{-1}s^{-1}$). In addition, we fabricated organic photovoltaic (OPV) cells with new 2-hexylthieno [3,2-b]thiophene-containing conjugated molecules and methanofullerene [6,6]-phenyl C61-butyric acid methyl ester ($PC_{61}BM$) without thermal annealing. The ternary system for a bulk heterojunction (BHJ) OPV cell was elaborated using $PC_{61}BM$ and two p-type conjugated molecules such as 5 and 7 for modulating the molecular energy levels. As a result, the OPV cell containing 5, 7, and $PC_{61}BM$ had improved results with an open-circuit voltage of 0.90 V, a short-circuit current density of 2.83 $mA/cm^2$, and a fill factor of 0.31, offering an overall power conversion efficiency (PCE) of 0.78%, which was larger than those of the devices made of only molecule 5 (${\eta}$~0.67%) or 7 (${\eta}$~0.46%) with $PC_{61}BM$ under identical weight compositions.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.722-725
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• 2012

In this paper, we design an 8-bit eSuse OTP (one-time programmable) memory based on a $0.35{\mu}m$ BCD process using differential paired eFuse cells which can sense BL data without a reference voltage and also have smaller sensing resistances of programmed eFuse links. The channel widths of a program transistor of the differential eFuse OTP cell are splitted into $45{\mu}m$ and $120{\mu}m$. Also, we implement a sensing margin test circuit with variable pull-up loads in consideration of variations of the programmed eFuse resistances. It is confirmed by measurement results that the designed 8-bit eFuse OTP memory IP gives a better yield when the channel width is $120{\mu}m$.

• Bulletin of the Korean Chemical Society
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• v.35 no.5
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• pp.1356-1364
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• 2014

A new conjugated copolymer, poly{4,8-bis(triisopropylsilylethynyl)benzo[1,2-b:4,5-b']dithiophene-alt-4,7- bis(5-thiophen-2-yl)-5,6-difluoro-2-(heptadecan-9-yl)-2H-benzo[d][1,2,3]triazole} (PTIPSBDT-DFDTBTz), is synthesized by Stille coupling polycondensation. The synthesized polymer has a band gap energy of 1.9 eV, and it absorbs light in the range 300-610 nm. The hole mobility of a solution-processed organic thin-film transistor fabricated using PTIPSBDT-DFDTBTz is $3.8{\times}10^{-3}cm^2V^{-1}s^{-1}$. Bulk heterojunction photovoltaic cells are fabricated, with a conventional device structure of ITO/PEDOT:PSS/polymer:$PC_{71}BM$/Ca/Al ($PC_{71}BM$ = [6,6]-phenyl-$C_{71}$-butyric acid methyl ester); the device shows a power conversion efficiency (PCE) of 2.86% with an open-circuit voltage ($V_{oc}$) of 0.85 V, a short-circuit current density ($J_{sc}$) of 7.60 mA $cm^{-2}$, and a fill factor (FF) of 0.44. Inverted photovoltaic cells with the structure ITO/ethoxylated polyethlyenimine/ polymer:$PC_{71}BM/MoO_3$/Ag are also fabricated; the device exhibits a maximum PCE of 2.92%, with a $V_{oc}$ of 0.89 V, a $J_{sc}$ of 6.81 mA $cm^{-2}$, and an FF of 0.48.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.279.1-279.1
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• 2016

박막 트랜지스터 (thin film transistor, TFT)는 고밀도, 대면적화로 높은 전자의 이동도가 요구되면서, 비정질 실리콘 (a-Si)에서 다결정 실리콘 (poly-Si) TFT 로 연구되었다. 이에 따라 비정질 실리콘에서 결정질 실리콘으로의 상변화에 대한 결정화 연구가 활발히 진행되었다. 또한, 박막 태양전지 분야에서도 유리기판 위에 비정질 층을 증착한 후에 열처리를 통해 상변화하는 고상 결정화 (solid-phase crystallization, SPC) 기술을 적용하여, CSG (thin-film crystalline silicon on glass) 태양전지를 보고하였다. 이러한 비정질 실리콘 층의 결정화 기술을 결정질 실리콘 태양전지 에미터 형성 공정에 적용하고자 한다. 이 때, 플라즈마화학증착 (Plasma-enhanced chemical vapor deposition, PECVD) 장비로 증착된 비정질 실리콘 층의 열처리를 통한 결정화 정도가 중요한 요소이다. 따라서, 비정질 실리콘 층의 결정화에 영향을 주는 인자에 대해 연구하였다. 비정질 실리콘 증착 조건(H2 가스 비율, 도펀트 유무), 실리콘 기판의 결정방향, 열처리 온도에 따른 결정화 정도를 엘립소미터(elipsometer), 투과전자현미경 (transmission electron microscope, TEM), 적외선 분광기 (Fourier Transform Infrared, FT-IR) 측정을 통하여 비교 하였다. 이를 기반으로 결정화 온도에 따른 비정질 실리콘의 결정화를 위한 활성화 에너지를 계산하였다. 비정질 실리콘 증착 조건 보다 기판의 결정방향이 결정화 정도에 크게 영향을 미치는 것으로 확인하였다.

• Korean Journal of Materials Research
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• v.21 no.3
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• pp.133-137
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• 2011

Gold have been used as an electrode materials having a good mechanical flexibility as well as electrical conductivity, however the stretchability of the gold on a flexible substrate is poor because of its small elastic modulus. To overcome this mechanical inferiority, the reinforcing gold is necessary for the stretchable electronics. Among the reinforcing materials having a large elastic modulus, carbon nanotube (CNT) is the best candidate due to its good electrical conductivity and nanoscale diameter. Therefore, similarly to ferroconcrete technology, here we demonstrated gold electrodes mechanically reinforced by inserting fabrics of CNTs into their bodies. Flexibility and stretchability of the electrodes were determined for various densities of CNT fabrics. The roles of CNTs in resisting electrical disconnection of gold electrodes from the mechanical stress were confirmed using field emission scanning electron microscope and optical microscope. The best mechanical stability was achieved at a density of CNT fabrics manufactured by 1.5 ml spraying. The concept of the mechanical reinforced metal electrode by CNT is the first trial for the high stretchable conductive materials, and can be applied as electrodes materials in various flexible and stretchable electronic devices such as transistor, diode, sensor and solar cell and so on.

• The Journal of the Korea Contents Association
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• v.7 no.2
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• pp.92-99
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• 2007

This paper presented a low power design of a 32bit block cypher processor reduced from the original 128bit architecture. The primary purpose of this research is to evaluate physical implementation results rather than theoretical aspects. The data path and diffusion function of the processor were reduced to accommodate the smaller hardware size. As a running example demonstrating the design approach, we employed a modified ARIA algorithm having four S-boxes. The proposed 32bit ARIA processor comprises 13,893 gates which is 68.25% smaller than the original 128bit structure. The design was synthesized and verified based on the standard cell library of the MagnaChip's 0.35um CMOS Process. A transistor level power simulation shows that the power consumption of the proposed processor reduced to 61.4mW, which is 9.7% of the original 128bit design. The low power design of the block cypher Processor would be essential for improving security of battery-less wireless sensor networks or RFID.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.109-114
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• 2013

Power MOSFET (metal-oxide semiconductor field-effect transistor) are widely used in power electronics applications, such as BLDC (Brushless Direct Current) motor and power module, etc. For the conventional power MOSFET device structure, there exists a tradeoff relationship between specific on-state resistance and breakdown voltage. In order to overcome the tradeoff relationship, a non-uniform super-junction (SJ) trench MOSFET (TMOSFET) structure for an optimal design is proposed in this paper. It is required that the specific on-resistance of non-uniform SJ TMOSFET is less than that of uniform SJ TMOSFET under the same breakdown voltage. The idea with a linearly graded doping profile is proposed to achieve a much better electric field distribution in the drift region. The structure modelling of a unit cell, the characteristic analyses for doping density, and potential distribution are simulated by using of the SILVACO TCAD 2D device simulator, Atlas. As a result, the non-uniform SJ TMOSFET shows the better performance than the uniform SJ TMOSFET in the specific on-resistance at the class of 100V.

• Journal of IKEEE
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• v.12 no.1
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• pp.1-7
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• 2008

With the recent development of portable system such as mobile communication and multimedia. Full adders are important components in applications such as digital signal processors and microprocessors. Thus It is important to improve the power dissipation and operating speed for designing a full adder. We propose a new adder with modified version of conventional Ratioed logic and Pass Transistor logic. The proposed adder has the advantages over the conventional CMOS, TGA, 14T logic. The delay time is improved by 13% comparing to the average value and PDP(Power Delay Product) is improved by 9% comparing to the average value. Layouts have been carried out using a 0.18um CMOS design rule for evaluation purposes. The physical design has been evaluated using HSPICE.