• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.62-65
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• 1998

This paper presents a method and implementation of the parallel distributed sample scrambler(DSS) in the cell-based ATM transmission environment. In the serial processing, it requires very high speed clock because the processing clock of the serial DSS is equal with the data transmission speed. In this paper, we develop a conversion method of the serial SRG(shift register generator) to 8bit parallel realization. In this case, it has a sample data processing problem which is a character of DSS. So, a theory of correction time movement is presented to solve this problem. We has developed a ASIC using this algorithm and verified the recommendation of ITU-T, I.432.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.990-991
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• 2008

본 논문에서는 절연형 풀브릿지 컨버터의 고조파 변압기 2차측을 직렬로 연결하여 스위칭 주파수 증대효과가 있는 새로운 전력변환기를 제안하였다. 제안된 컨버터는 기존 방식에 비해 정류부와 필터부의 일원화가 가능한 구조로 수동소자의 수를 대폭 줄일 수 있다. 또한 제안된 전력변환기 구조에서 출력전압의 리플과 높은 승압비를 유지하기 위한 새로운 가변 위상 변위형 스위칭 방식을 제안하였다.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2224-2236
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• 2014

The performance of an isolated high voltage full bridge converter is improved using a voltage doubler. In a conventional high voltage full bridge converter, the diode of the transformer secondary voltage undergoes a voltage spike due to the leakage inductance of the transformer and the resonance occurring with the parasitic capacitance of the diode. In addition, in the phase shift control, conduction loss largely increases from the freewheeling mode because of the circulating current. The efficiency of the converter is thus reduced. However, in the proposed converter, the high voltage dual converter consists of a voltage doubler because the circulating current of the converter is reduced to increase efficiency. On the other hand, in the proposed converter, an input current is distributed when using parallel input / serial output and the output voltage can be doubled. However, the voltages in the 2 serial DC links might be unbalanced due to line impedance, passive and active components impedance, and sensor error. Considering these problems, DC injection is performed due to the complementary operations of half bridge inverters as well as the disadvantage of the unbalance in the DC link. Therefore, the serial output of the converter needs to control the balance of the algorithm. In this paper, the performance of the conventional converter is improved and a balance control algorithm is proposed for the proposed converter. Also, the system of the 1.5[kW] PCS is verified through an experiment examining the operation and stability.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.10
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• pp.2283-2291
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• 2010

The shrinking generator which is one of clock-controlled generator is a very simple generator with good cryptographic properties. A nonlinear sequence generator based on two 90/150 maximum length cellular automata can generate pseudorandom sequences at each cell of cellular automata whose characteristic polynomials are same. The nonlinear sequence generated by cellular automata has a larger period and a higher linear complexity than shrunken sequence generated by LFSRs. In this paper we analyze shrunken-interleaved sequence based on 90/150 maximum length cellular automata. We show that the sequence generated by nonlinear sequence generator based on cellular automata belongs to the class of interleaved sequence. And we give an effective algorithm for reconstructing unknown bits of output sequence based on intercepted keystream bits.

• Journal of Korea Multimedia Society
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• v.13 no.7
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• pp.943-949
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• 2010

This paper presents some improvements on VLSI implementation of lifting-based 9/7 wavelet transform by optimization hardware multiplication. The proposed solution requires less logic area and power consumption without performance loss compared to previous wavelet filter structure based on lifting scheme. This paper proposes a better approach to the hardware implementation using Lefevre algorithm based on extensions of Pattern search methods. To compare the proposed structure to the previous solutions on full multiplier blocks, we implemented them using Verilog HDL. For a hardware implementation of the two solutions, the logical synthesis on 0.18 um standard cells technology show that area, maximum delay and power consumption of the proposed architecture can be reduced up to 51%, 43% and 30%, respectively, compared to previous solutions for a 200 MHz target clock frequency. Our evaluation show that when design VLSI chip of lifting-based 9/7 wavelet filter, our solution is better suited for standard-cell application-specific integrated circuits than prior works on complete multiplier blocks.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.3
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• pp.244-249
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• 2010

The design of error correction code with low complexity has a good attraction for next generation multi-level cell flash memory. Sharing sub-expressions is effective method to reduce complexity and chip size. This paper proposes a new design method of m-bit parallel BCH encoder based on serial linear feedback shift register structure with low complexity using sub-expression. In addition, general algorithm for obtaining the sub-expression is introduced. The sub-expression can be expressed by matrix operation between sub-matrix of generator matrix and sum of two different variables. The number of the sub-expression is restricted by. The obtained sub-expressions can be shared for implementation of different m-parallel BCH encoder. This paper is not focused on solving a problem (delay) induced by numerous fan-out, but complexity reduction, expecially the number of gates.