• Title/Summary/Keyword: Cell Boundary

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Identification of boundary migration during the wound healing through the visualization of cell migrations (세포 운동 가시화를 통한 상처 치유 과정 내 경계 이동의 규명)

  • Jeong, Hyuntae;Lee, Jaesung;Shin, Jennifer Hyunjong
    • Journal of the Korean Society of Visualization
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    • v.18 no.2
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    • pp.10-17
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    • 2020
  • The curvature of wound boundaries has been identified as a key modulator that determines a type of force responsible for cell migration. While several studies report how certain curvatures of the boundary correlate with the rate at which the wound closes, it remains unclear how these curvatures are spatiotemporally formed to regulate the healing process. We investigated the dynamic changes in the boundary curvatures by visualizing cell migration patterns. Locally, cells at the convex boundary continuously move forward with transmitting kinetic responses behind to the cells away from the boundary, and cells at the concave boundary exhibit dramatic contracting motion, like a purse-string, when they accumulate enough negative curvatures to gain the thrust toward the void. Globally, the dynamics of boundary geometries are controlled by the diffusive flow of cells driven by the density gradient between the wound area and the cell layer.

Analysis of Grain Boundary Effects in Poly-Si Wafer for the Fabrication of Low Cost and High Efficiency Solar Cells (저가 고효율 태양전지 제작을 위한 다결정 실리콘 웨이퍼 결정입계 영향 분석)

  • Lee, S.E.;Lim, D.G.;Kim, H.W.;Kim, S.S.;Yi, J.
    • Proceedings of the KIEE Conference
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    • 1998.07d
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    • pp.1361-1363
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    • 1998
  • Poly-Si grain boundaries act as potential barriers as well as recombination centers for the photo-generated carriers in solar cells. Thereby, grain boundaries of poly-Si are considered as a major source of the poly-Si cell efficiency was reduced This paper investigated grain boundary effect of poly-Si wafer prior to the solar cell fabrication. By comparing I-V characteristics inner grain, on and across the grain boundary, we were able to detect grain potentials. To reduce grain boundary effect we carried out pretreatment, $POCl_3$ gettering, and examined carrier lifetime. This paper focuses on resistivity variation effect due to grain boundary of poly-Si. The resistivity of the inner grain was $2.2{\Omega}-cm$, on the grain boundary$2.3{\Omega}-cm$, across the grain boundary $2.6{\Omega}-cm$. A measured resistivity varied depending on how many grains were included inside the four point probes. The resistivity increased as the number of grain boundaries increased. Our result can contribute to achieve high conversion efficiency of poly-Si solar cell by overcoming the grain boundary influence.

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Development of Viscous Boundary Conditions in an Immersed Cartesian Grid Framework

  • Lee, Jae-Doo
    • Journal of Ship and Ocean Technology
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    • v.10 no.3
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    • pp.1-16
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    • 2006
  • Despite the high cost of memory and CPU time required to resolve the boundary layer, a viscous unstructured grid solver has many advantages over a structured grid solver such as the convenience in automated grid generation and vortex capturing by solution adaption. In present study, an unstructured Cartesian grid solver is developed on the basis of the existing Euler solver, NASCART-GT. Instead of cut-cell approach, immersed boundary approach is applied with ghost cell boundary condition, which can be easily applied to a moving grid solver. The standard $k-{\varepsilon}$ model by Launder and Spalding is employed for the turbulence modeling, and a new wall function approach is devised for the unstructured Cartesian grid solver. Developed approach is validated and the efficiency of the developed boundary condition is tested in 2-D flow field around a flat plate, NACA0012 airfoil, and axisymmetric hemispheroid.

A study on efficiency improvement of poly-Si solar cell using a selective etching along the grain boundaries (결정입계 선택적 식각 기법을 적용한 다결정 규소 태양전지의 효율 향상에 관한 연구)

  • 임동건;이수은;박성현;이준신
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1999.05a
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    • pp.597-600
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    • 1999
  • A solar cell conversion efficiency was degraded by grain boundary effect in polycrystalline silicon To reduce grain boundary effect, we performed a preferential grain boundary etching, POC$_3$ n-type emitter doping, and then ITO film growth on poly- Si. Among the various preferential etchants, Schimmel etch solution exhibited the best result having grain boundary etch depth higher than 10 ${\mu}{\textrm}{m}$. RF magnetron sputter grown ITO films showed a low resistivity of 10$^{-4}$ $\Omega$ -cm and high transmittance of 85 %. With well fabricated poly-Si solar cells, we were able to achieve as high as 15 % conversion efficiency at the input power of 20 mW/$\textrm{cm}^2$.

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Delay Test for Boundary-Scan based Architectures (경계면 스캔 기저 구조를 위한 지연시험)

  • 강병욱;안광선
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.6
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    • pp.199-208
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    • 1994
  • This paper proposes a delay fault test technique for ICs and PCBs with the boundary-scan architectures supporting ANSI/IEEE Std 1149.1-1990. The hybrid delay fault model, which comprises both of gate delay faults and path delay faults, is selected. We developed a procedure for testing delay faults in the circuits with typical boundary scan cells supporting the standard. Analyzing it,we concluded that it is impractical because the test clock must be 2.5 times faster than the system clock with the cell architect-ures following up the state transition of the TAP controller and test instruction set. We modified the boundary-scan cell and developed test instructions and the test procedure. The modified cell and the procedure need test clock two times slower than the system clock and support the ANSI/IEEE standard perfectly. A 4-bit ALU is selected for the circuits under test. and delay tests are simulated by the SILOS simulator. The simulation results ascertain the accurate operation and effectiveeness of the modified mechanism.

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Smooth Boundary Topology Optimization Using B-spline and Hole Generation

  • Lee, Soo-Bum;Kwak, Byung-Man;Kim, Il-Yong
    • International Journal of CAD/CAM
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    • v.7 no.1
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    • pp.11-20
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    • 2007
  • A topology optimization methodology, named "smooth boundary topology optimization," is proposed to overcome the shortcomings of cell-based methods. Material boundary is represented by B-spline curves and their control points are considered as design variables. The design is improved by either creating a hole or moving control points. To determine which is more beneficial, a selection criterion is defined. Once determined to create a hole, it is represented by a new B-spline and recognized as a new boundary. Because the proposed method deals with the control points of B-spline as design variables, their total number is much smaller than cell-based methods and it ensures smooth boundaries. Differences between our method and level set method are also discussed. It is shown that our method is a natural way of obtaining smooth boundary topology design effectively combining computer graphics technique and design sensitivity analysis.

Evaluation of Effective In-Plane Elastic Properties by Imposing Periodic Displacement Boundary Conditions (주기적 변형 경계조건을 적용한 면내 유효 탄성 물성치의 계산)

  • 정일섭
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.28 no.12
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    • pp.1950-1957
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    • 2004
  • Analysis for structures composed of materials containing regularly spaced in-homogeneities is usually executed by using averaged material properties. In order to evaluate the effective properties, a unit cell is defined and loaded somehow, and its response is investigated. The imposed loading, however, should accord to the status of unit cells immersed in the macroscopic structure to secure the accuracy of the properties. In this study, mathematical description for the periodicity of the displacement field is derived and its direct implementation into FE models of unit cell is attempted. Conventional finite element code needs no modification, and only the boundary of unit cell should be constrained in a way that the periodicity is preserved. The proposed method is applicable to skew arrayed in-homogeneity problems. Homogenized in-plane elastic properties are evaluated for a few representative cases and the accuracy is examined.

Study on Numerical Analysis Method for Moving Boundary of Interior Ballistics (강내탄도의 이동경계면 해석을 위한 수치해석 기법 연구)

  • Kim, In-Joo;Jang, Jin-Sung;Sung, Hyung-Gun;Roh, Tae-Seong
    • Proceedings of the Korean Society of Propulsion Engineers Conference
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    • 2010.11a
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    • pp.760-763
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    • 2010
  • The expansion of 1D numerical code to 2D or 3D is needed in order to improve the analysis accuracy of the interior ballistics. The cut cell method has been imposed for the code expansion to multi dimensions. The MUSCL-Hancock scheme as a high resolution method has been selected. A feasibility of the cut cell method has been verified by analyzing the free piston problem.

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Area Measurement of Organism Image using Super Sampling and Interpolation (수퍼 샘플링과 보간을 이용한 생물조직 영상의 면적 측정)

  • Choi, Sun-Wan;Yu, Suk-Hyun
    • Journal of Korea Multimedia Society
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    • v.17 no.10
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    • pp.1150-1159
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    • 2014
  • This paper proposes a method for extracting tissue cells from an organism image by an electron microscope and getting the whole cell number and the area from the cell. In general, the difference between the cell color and the background is used to extract tissue cell. However, there may be a problem when overlapped cells are seen as a single cell. To solve the problem, we split them by using cell size and curvature. This method has a 99% accuracy rate. To measure the cell area, we compute two areas, the inside and boundary of the cell. The inside is simply calculated by the number of pixels. The cell boundary is obtained by applying super sampling, linear interpolation, and cubic spline interpolation. It improves the error rate, 18%, 19%, and 120% respectively, in comparison to the counting method that counts a pixel area as 1.

A Design of FPGA Self-test Circuit Reusing FPGA Boundary Scan Chain (FPGA 경계 스캔 체인을 재활용한 FPGA 자가 테스트 회로 설계)

  • Yoon, Hyunsik;Kang, Taegeun;Yi, Hyunbean
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.6
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    • pp.70-76
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    • 2015
  • This paper introduces an FPGA self-test architecture reusing FPGA boundary scan chain as self-test circuits. An FPGA boundary scan cell is two or three times bigger than a normal boundary scan cell because it is used for configuring the function of input/output pins functions as well as testing and debugging. Accordingly, we analyze the architecture of an FPGA boundary scan cell in detail and design a set of built-in self-test (BIST) circuits in which FPGA boundary scan chain and a small amount of FPGA logic elements. By reusing FPGA boundary scan chain for self-test, we can reduce area overhead and perform a processor based on-board FPGA testing/monitoring. Experimental results show the area overhead comparison and simulation results.