• ETRI Journal
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• v.38 no.1
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• pp.133-140
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• 2016

This paper presents a method of parasitic inductance reduction for high-speed switching and high-efficiency operation of a cascode structure with a low-voltage enhancement-mode silicon (Si) metal-oxide-semiconductor field-effect transistor (MOSFET) and a high-voltage depletion-mode gallium nitride (GaN) fielde-ffect transistor (FET). The method is proposed to add a bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in a conventional cascode structure package to reduce the most critical inductance, which provides the major switching loss for a high switching speed and high efficiency. From the measured results of the proposed and conventional GaN cascode FETs, the rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. During the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively.

• ETRI Journal
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• v.39 no.1
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• pp.62-68
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• 2017

In this paper, we present the design and characterization analysis of a cascode GaN field-effect transistor (FET) for switching power conversion systems. To enable normally-off operation, a cascode GaN FET employs a low breakdown voltage (BV) enhancement-mode Si metal-oxide-semiconductor FET and a high-BV depletion-mode (D-mode) GaN FET. This paper demonstrates a normally-on D-mode GaN FET with high power density and high switching frequency, and presents a theoretical analysis of a hybrid cascode GaN FET design. A TO-254 packaged FET provides a drain current of 6.04 A at a drain voltage of 2 V, a BV of 520 V at a drain leakage current of $250{\mu}A$, and an on-resistance of $331m{\Omega}$. Finally, a boost converter is used to evaluate the performance of the cascode GaN FET in power conversion applications.

• Journal of IKEEE
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• v.26 no.4
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• pp.553-559
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• 2022

In this paper, RC snubber circuit design technology for oscillation suppression in half-bridge configuration of cascode gallium nitride (GaN) field effect transistors (FETs) is analyzed. A typical wide band-gap (WBG) device, cascode GaN FET, has excellent high-speed switching characteristics. However, due to such high-speed switching characteristics, a false turn-off problem is caused, and an RC snubber circuit is essential to suppress this. In this paper, the commonly used experimental-based RC snubber design technique and the RC snubber design technique using the root locus method are compared and analyzed. In the general method, continuous circuit changes are required until the oscillation suppression performance requirement is met based on experimental experience . However, in root locus method, the initial value can be set based on the non-oscillation R-C map. To compare the performance of the two aforementioned design methods, a simulation experiment and a switching experiment using an actual double pulse circuit are performed.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.5
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• pp.472-478
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• 2003

In this paper, a near zero If mixer was designed in cascode structure by using two single-gate FETs. Since it is driven by the second order harmonic of LO signal, a sub-harmonic cascode FET mixer has good LO-RF port isolation characteristic. In order to solve DC offset of a homodyne system, near zero If is used instead of zero If and the mixer is driven by sub-harmonic of LO signal. As RF input power was -30 dBm and LO power was 6 dBm, the designed mixer had 6.7 dB conversion gain, 8.4 dB noise figure, 31.5 dB LO-RF port isolation, -1.9 dBm lIP3 and -2.8 dBm IIP2.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.93-96
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• 2003

본 논문은 캐스코드 구조에서의 바이어스 조건에 대해 분석하고 이를 이용하여 C-Band용 마이크로파 수신기에서의 자기발진믹서를 분석하였다. 자기발진믹서는 두 개의 FET에 의해서 동작되며 상위 FET는 비교적 높은 Q값을 가지는 유전체공진기에 의해서 발진기로 동작하도록 하였으며, 아래쪽 FET는 믹서로 동작시켰다. 모의실험 결과에 의해 초기 드레인 전압은 $V_{ds}$ =2.5V이고 게이트바이어스 전압은 $V_{gs1}$=-0.2V와 $V_{g2}$=0V로 선정하였다. 선정된 바이어스를 통해 설계된 5.15GHz의 발진기 출력은 5.92dBm, 위상잡음은 -132.0dBc/100KHz, 믹서의 변환손실은 약 -3dB를 얻었다.얻었다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.3
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• pp.492-498
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• 2003

In this paper, We analyze the optimum bias conditions of cascode coupled microwave mixer for maximum conversion gain mixer. Microwave self-oscillating mixer by two GaAs MESFET cascode coupled, to upper GaAs MESFET operating as a oscillator with high Q dielectric resonator and the lower GaAs MESFET operated as a mixer with low noise and high conversion characteristics. As a result of experiments, cascode coupled microwave self oscillating mixer according to optimun bias shows an 5.92 dBm oscillating power, -132.0dBc/Hz @ 100KHz at 5.15GHz and 3dB conversion loss.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1046-1049
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• 2002

In this paper, a sub-harmonic dual-gate FET mixer for IMT-2000 base-station was designed by using single-gate FET cascode structure and driven by the second order harmonic component of LO signal. The dual-gate FET mixer has the characteristic of high conversion gain and good isolation between ports. Sub-harmonic mixing is frequently used to extend RF bandwidth for fixed LO frequency or to make LO frequency lower. Furthermore, the LO-to-RF isolation characteristic of a sub-harmonic mixer is better than that of a fundamental mixer because the frequency separation between the RE and LO frequency is large. As RF power is -30dBm and LO power is 0dBm, the designed mixer shows the -47.17dBm LO-to-RF leakage power level, 10dB conversion gain, -0.5dBm OIP3, -10.5dBm IIP3 and -1dBm 1dB gain compression point.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.11
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• pp.1633-1640
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• 2013

In this paper, noise parameters for high frequency modeling of dual-gate FET are extracted and analyzed. To extract thermal noise parameter of dual gate, noise characteristics are measured by changing input impedance of noise source using Tuner, and the influence of pad parasitic elements are subtracted using open and short dummy structure. Measured results indicated that the dual-gate FET is improved the noise figure by 0.2dB compared with conventional cascode structure FET at 5GHz, and it confirmed that the noise figure has dropped due to reduction of capacitances between the drain and source, gate and drain by simulation and analysis of small-signal parameters.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.7 s.361
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• pp.41-46
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• 2007

A novel post-linearization technique is proposed for CMOS cascode low noise amplifier (LNA). The technique uses dual common gate FETs one of which delivers the linear currents to a load and the other one sinks the $3^{rd}$ order intermodulation currents of output currents from the common source FET. Selective current branching can be implemented in $0.18{\mu}m$ CMOS process by using a thick oxide FET as an IM3 sinker with a normal FET as a linear current buffer. A differential LNA adopting this technique is designed at 2.14GHz. The measurement results show 11dBm IIP3, 15.5dB power gain and 2.85dB noise figure consuming 12.4mA from 1.8V power supply. Compared with the LNA with turning off the IM3 sinker, the proposed technique improves the IIP3 by 7.5 dB.

• Journal of Advanced Navigation Technology
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• v.10 no.2
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• pp.138-144
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• 2006

In this paper, dual mode FET mixer for WiBro and wireless LAN(WLAN) applications has been designed in the form of dual gate FET mixer by using the cascode structure of two single gate pHEMTs. The designed dual gate mixer has been optimized to have variable conversion gain for WiBro and WLAN applications in order to save dc power consumption. The LO to RF isolation of the designed mixer is more than 20dB from 2.3GHz to 2.5GHz band. With the LO power of 0dBm and RF power of -50dBm, the mixer shows 15dB conversion gain. When RF power increases from -50dBm to -20dBm, the conversion gain decreases to -2dB from 15dB with bias change. The variable conversion gain has several advantages. It can reduce the high dynamic range requirement of AGC burden at IF stage. Also, it can save the dc power dissipation of mixer up to 90%.