• Journal of Electrical Engineering and Technology
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• 제7권1호
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• pp.81-85
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• 2012

This paper presents a wideband and low-noise direct conversion front-end receiver supporting VHF and UHFbands simultaneously. The receiver iscomposed of a low-noise amplifier (LNA), a down conversion quadrature mixer, and a frequency divider by 2. The cascode configuration with the resistor feedback is exploited in the LNA to achieve a wide operating bandwidth. Four gainstep modesare employed using a switched resistor bank and a capacitor bank in the signal path to cope with wide dynamic input power range. The verticalbipolar junction transistors are used as the switching elements in the mixer to reduce 1/f noise corner frequency. The proposed front-end receiver fabricated in 0.18 ${\mu}m$ CMOS technology shows very low minimum noise figureof 1.8 dB and third order input intercept pointof -12dBm inthe high-gain mode of 26.5 dBmeasured at 500 MHz.The proposed receiverconsumeslow current of 20 mA from a 1.8 V power supply.

• 대한전기학회논문지:전력기술부문A
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• 제48권4호
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• pp.461-466
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• 1999

A CMOS op amp with rail-to-rail input and output ranges is designed in a one-volt supply. The output stage of the op amp is used in a common source amplifier that operates in sub-threshold region to design a low voltage op amp with rail-to-tail output range. To drive heavy resistor and capacitor loads with rail-to-rail output ranges, a common source amplifier which has a low output resistance is utilized. A bulk-driven differential pair and a bulk-driven folded cascode amplifier are used in the designed op amp to increase input range and achieve 1 V operation. Post layout simulation results show that low frequency gain is about 58 ㏈ and gain bandwidth I MHz. The designed op amp has been fabricated in a 0.8${\mu}{\textrm}{m}$ standard CMOS process. The measured results show that this op amp provides rail-to-rail output range, 56㏈ dc gain with 1 MΩ load and has 0.4 MHz gain-bandwidth with 130 ㎊ and 1 kΩ loads.

• 한국전자통신학회논문지
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• 제8권11호
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• pp.1633-1640
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• 2013

본 논문에서는 이중게이트 FET를 고주파회로에 응용하기 위해 필요한 열잡음 파라미터를 추출하여 그 특성을 분석하였다. 이중게이트 열잡음 파라미터를 추출하기 위해 튜너를 이용해 잡음원의 임피던스를 바꿔가며 잡음특성을 측정하였으며, open과 short 더미를 이용해서 패드의 기생성분을 제거하였다. 측정결과 일반적인 캐스코드구조의 FET와 비교해서 5GHz에서 약 0.2dB의 잡음 개선효과가 있음을 확인하였으며, 시뮬레이션과 소신호 파라미터 분석을 통해 드레인 소스 및 드레인 게이트간 캐패시턴스의 감소에 의해 잡음지수가 줄어들었음을 확인하였다.

• Transactions on Electrical and Electronic Materials
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• 제2권4호
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• pp.1-6
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• 2001

In this paper, a 1.5 V high-gain high-frequency CMOS complementary operational amplifier is presented. The input stage of op-amp is designed for supporting the constant transconductance on the Input stage by consisting of the parallel-connected rail-to-rail complementary differential pairs. And consisting of the class-AB rail-to-rail output stage using the concept of elementary shunt stage and the grounded-gate cascode compensation technique for improving the low PSRR which was a disadvantage in the general CMOS complementary input stage, the load dependence of open loop gain and the stability of op- amp on the output load are improved, and the high-gain high-frequency operation can be achieved. The designed op-amp operates perfectly on the complementary mode with the 180° phase conversion for a 1.5 V supply voltage, and shows the DC open loop gain of 84 dB, the phase margin of 65°, and the unity gain frequency of 20 MHz. In addition, the amplifier shows the 0.1 % settling time of .179 ㎲ for the positive step and 0.154 ㎲ for the negative step on the 100 mV small-signal step, respectively, and shows the total power dissipation of 8.93 mW.

• 전기학회논문지
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• 제64권12호
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• pp.1730-1736
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• 2015

This paper presents a 16-channel transimpedance amplifier (TIA) array implemented in a standard $0.18-{\mu}m$ CMOS technology for the applications of panoramic scan LADAR (PSL) systems. Since this array is the front-end circuits of the PSL systems to recover three dimensional image for unmanned vehicles, low-noise and high-gain characteristics are necessary. Thus, we propose a voltage-mode inverter TIA (I-TIA) array in this paper, of which measured results demonstrate that each channel of the array achieves $82-dB{\Omega}$ transimpedance gain, 565-MHz bandwidth for 0.5-pF photodiode capacitance, 6.7-pA/sqrt(Hz) noise current spectral density, and 33.8-mW power dissipation from a single 1.8-V supply. The measured eye-diagrams of the array confirm wide and clear eye-openings up to 1.3-Gb/s operations. Also, the optical pulse measurements estimate that the proposed 16-channel TIA array chip can detect signals within 20 meters away from the laser source. The whole chip occupies the area of $5.0{\times}1.1mm^2$ including I/O pads. For comparison, a current-mode 16-channel TIA array is also realized in the same $0.18-{\mu}m$ CMOS technology, which exploits regulated-cascode (RGC) input configuration. Measurements reveal that the I-TIA array achieves superior performance in optical pulse measurements.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2006년도 춘계종합학술대회
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• pp.906-909
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• 2006

본 논문은 저 전압 및 저 왜곡 스위치형 커패시터 (switched-capacitor, SC)를 적용한 새로운 형태의 몸체효과 보상형 스위치 구조를 제안한다 제안된 회로는 저 전압 SC 회로를 위해서 rail-to-rail 스위칭을 허용하며 기존의 부트스트랩된 회로 (19dB) 보다 더 우수한 총 고조파 왜곡을 가진다. 설계된 2-1 캐스케이드 시그마 델타 변조기는 통신 송수신시스템내의 오디오 코덱을 위한 고해상도 아날로그-디지털변환을 수행한다. 1단 폴드형 캐스코드 연산증폭기 및 2-1 캐스케이드 시그마 델타 변조기는 0.25 마이크론 이중 폴리 3-금속 표준 CMOS 공정으로 제작되었으며, 2.7V에서 동작한다.

• 한국멀티미디어학회논문지
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• 제6권2호
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• pp.319-324
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• 2003

본 논문에서는 음성과 영상신호를 실시간 처리해야하는 멀티미디어 시스템에 이용 가능한 광대역 아날로그 소자를 설계하였다. 제안된 소자는 저 전압(2V) 동작이 가능하도록 완전차동 구조에 전압조절을 위한 튜닝회로를 추가한 형태로 설계되었으며, 이득특성에 영향을 주는 트랜스컨덕턴스값을 증가시키기 위해 상보형 캐스코드 방식을 이용하여 구성되었다. 0.25$\mu\textrm{m}$ CMOS n-well 공정 파라미터를 이용한 시뮬레이션 결과, 제안된 아날로그 능동소자는 비우성극점의 제거로 안정성이 향상되었으며, 2V 공급전압하에서 42dB의 이득값과 200MHz의 단위 이득주파수 특성을 나타내었다. 소비전력값은 0.32mW를 나타내었다.

• Journal of the Optical Society of Korea
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• 제17권1호
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• pp.44-49
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• 2013

A transimpedance amplifier (TIA)-optical receiver (Rx) using two intersecting active feedback system with regulated-cascode (RGC) input stage has been designed and implemented for optical interconnects. The optical TIA-Rx chip is designed in a 0.13 ${\mu}m$ CMOS technology and works up to 10 Gbps data rate. The TIA-Rx chip core occupies an area of 0.051 $mm^2$ with power consumption of 16.9 mW at 1.3 V. The measured input-referred noise of optical TIA-Rx is 20 pA/${\surd}$Hz with a 3-dB bandwidth of 6.9 GHz. The proposed TIA-Rx achieved a high gain-bandwidth product per DC power figure of merit of 408 $GHz{\Omega}/mW$.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2019년도 전력전자학술대회
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• pp.83-85
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• 2019

The use of high voltage gain converters is essential for the distributed power generation systems with renewable energy sources such as the fuel cells and solar cells due to their low voltage characteristics. In this paper, a high voltage gain topology combining cascode Inverting Buck-Boost converter and voltage multiplier structure is introduced. In proposed converter, the input voltage is connected in series at the output, the portion of input power is directly delivered to the load which results in continuous input current. In addition, the voltage multiplier stage stacked in proper manner is not only enhance high step-up voltage gain ratio but also significantly reduce the voltage stress across all semiconductor devices and capacitors. As a result, the high current-low voltage switches can be employed for higher efficiency and lower cost. In order to show the feasibility of the proposed topology, the operation principle is presented and the steady-state characteristic is analyzed in detail. A 380W-40/380V prototype converter was built to validate the effectiveness of proposed converter.

• 전자공학회논문지C
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• 제36C권8호
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• pp.10-21
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• 1999

본 논문에서는 12비트의 해상도와 65MHz의 변환속도를 가지면서 단일 3.3V의 공급전압으로 동작하는 전류 셀 매트릭스 구조의 CMOS D/A 변환기를 제안하였다. 설계된 CMOS D/A 변환기는 우수한 단조증가성과 빠른 정착시간을 가지는 전류 셀 매트릭스 구조의 장점을 이용하면서 기존의 D/A 변환기의 전류셀 간의 문턱전압의 부정합과 접지선의 전압 강하에 의한 오차를 감소시키기 위해 트리 구조 바이어스 회로, 대칭적 접지선 연결, 캐스코드 전류 스위치를 사용하여 구현되었다. 설계된 전류 셀 매트릭스 12비트 D/A 변환기를 $0.6{\mu}m$ CMOS n-well 공정을 이용하여 제작하였다. 제작된 DAC칩을 +3.3V 단일 공급전원을 이용하여 측정한 결과, 정착시간이 20nsec로써 50MHz의 변환속도와 35.6mW의 전력소모를 나타내었다. 또한 측정된 SNR, DNL은 각각 55 dB, ${\pm}0.5LSB$,${\pm}2LSB$를 나타내었다.