• Current Optics and Photonics
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• v.2 no.5
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• pp.407-412
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• 2018

An optimal matching approach is proposed to maximally ensure the output power uniformity of the cascaded encoder in the passive optical network (PON) monitoring system based on a remote coding scheme. The calculation results show that the optimum arrangement can effectively reduce the difference of the total insertion loss in comparison to the random arrangement (i.e., 0.07 dB vs 2.67 dB in the cascaded encoder with 16 output ports). The proposed approach realizes the optimum configuration for the $1{\times}2$ optical splitters used without adding any extra components. The test results of the fabricated cascaded encoder with 32 output ports prove the feasibility of the proposed approach.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.1-10
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• 2006

In this paper, an 1.8V 8-bit 500MSPS CMOS A/D Converter is proposed. In order to obtain the resolution of 8bits and high-speed operation, a Cascaded-Folding Cascaded-Interpolation type architecture is chosen. For the purpose of improving SNR, Cascaded-folding Cascaded-interpolation technique, distributed track and hold are included [1]. A novel folding circuit, a novel Digital Encoder, a circuit to reduce the Reference Fluctuation are proposed. The chip has been fabricated with a $0.18{\mu}m$ 1-poly 5-metal n-well CMOS technology. The effective chip area is $1050{\mu}m{\times}820{\mu}m$ and it dissipates about 146mW at 1.8V power supply. The INL and DNL are within ${\pm}1LSB$, respectively. The SNDR is about 43.72dB at 500MHz sampling frequency.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.18 no.3
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• pp.653-669
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• 2024

Dynamic scene deblurring is a complex computer vision problem owing to its difficulty to model mathematically. In this paper, we present a novel approach for image deblurring with the help of the sharp reference image, which utilizes the reference image for high-quality and high-frequency detail results. To better utilize the clear reference image, we develop an encoder-decoder network and two novel modules are designed to guide the network for better image restoration. The proposed Reference Extraction and Aggregation Module can effectively establish the correspondence between blurry image and reference image and explore the most relevant features for better blur removal and the proposed Spatial Feature Fusion Module enables the encoder to perceive blur information at different spatial scales. In the final, the multi-scale feature maps from the encoder and cascaded Reference Extraction and Aggregation Modules are integrated into the decoder for a global fusion and representation. Extensive quantitative and qualitative experimental results from the different benchmarks show the effectiveness of our proposed method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.13-20
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• 2008

In this paper, an 1.8V 12-bit 10MSPS CMOS A/D converter (ADC) is described. The architecture of the proposed ADC is based on a folding and interpolation using an even folding technique. For the purpose of improving SNR, cascaded-folding cascaded-interpolation technique, distributed track and hold are adapted. Further, a digital encoder algorithm is proposed for efficient digital process. The chip has been fabricated with $0.18{\mu}m$ 1-poly 4-metal n-well CMOS technology. The effective chip area is $2000{\mu}m{\times}1100{\mu}m$ and it consumes about 250mW at 1.8V power supply. The measured SNDR is about 46dB at 10MHz sampling frequency.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.5
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• pp.24-28
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• 1985

In this paper, the cyclic product codes which are capable of correcting random erros and burst errors simultaneously have been designed and constructed. First, the procedure for product of two cyclic codes is shown and thin the encoder and decoder system using the (7,4) cyclic Hamming code and the (3,1) cyclic code is implemented. The micro-computer is used for experiment and the system consists of encoder, decoder and interface circuits. The encoder of cyclic product code is implemented by interlacing encoders while the decoder is implemented by cascading decoders that interlace error trapping decoders. In conclusion, cyclic product codas are easily decodable and are capable of correcting four random errors and eight-burst errors. Better performance is obtained with low error rate.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.318-325
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• 2008

A 1.2 V 7-bit 1 GS/s CMOS flash ADC with an interpolation factor of 4 is implemented by using a $0.13\;{\mu}m$ CMOS process. A digital calibration of DC reference voltage is proposed for the $1^{st}$ preamp array to compensate for the input offset voltage of differrential amplifiers without disturbing the high-speed signal path. A 3-stage cascaded voting process is used in the digital encoder block to eliminate the conescutive bubbles up to seven completely, if the $2^{nd}$ preamp output is assumed to have a single bubble at most. ENOB and the power consumption were measured to be 5.88 bits and 212 mW with a 195 MHz $400\;mV_{p-p}$ sine wave input.

• Smart Structures and Systems
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• v.29 no.1
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• pp.221-235
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• 2022

Manual inspection of steel box girders on long span bridges is time-consuming and labor-intensive. The quality of inspection relies on the subjective judgements of the inspectors. This study proposes an automated approach to detect and segment cracks in high-resolution images. An end-to-end cascaded framework is proposed to first detect the existence of cracks using a deep convolutional neural network (CNN) and then segment the crack using a modified U-Net encoder-decoder architecture. A Naïve Bayes data fusion scheme is proposed to reduce the false positives and false negatives effectively. To generate the binary crack mask, first, the original images are divided into 448 × 448 overlapping image patches where these image patches are classified as cracks versus non-cracks using a deep CNN. Next, a modified U-Net is trained from scratch using only the crack patches for segmentation. A customized loss function that consists of binary cross entropy loss and the Dice loss is introduced to enhance the segmentation performance. Additionally, a Naïve Bayes fusion strategy is employed to integrate the crack score maps from different overlapping crack patches and to decide whether a pixel is crack or not. Comprehensive experiments have demonstrated that the proposed approach achieves an 81.71% mean intersection over union (mIoU) score across 5 different training/test splits, which is 7.29% higher than the baseline reference implemented with the original U-Net.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.61-69
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• 2010

In this paper, an 1.2V 8b 800MSPS A/D Converter(ADC) with an odd number of folding block to overcome the asymmetrical boundary-condition error is described. The architecture of the proposed ADC is based on a cascaded folding architecture using resistive interpolation technique for low power consumption and high input frequency. The ADC employs a novel odd folding block to improve the distortion of signal linearity and to reduce the offset errors. In the digital block, furthermore, we use a ROM encoder to convert a none-$2^n$-period code into the binary code. The chip has been fabricated with an $0.13{\mu}m$ 1P6M CMOS technology. The effective chip area is $870{\mu}m\times980{\mu}m$. SNDR is 44.84dB (ENOB 7.15bit) and SFDR is 52.17dBc, when the input frequency is 10MHz at sampling frequency of 800MHz.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.6
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• pp.91-99
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• 2004

This paper proposed two transcodiing methods, which maintain the same spatio-temporal resolution and reduce a spatial resolution, to convert a H.264 video bitstream into an MPEG-4 video bitstream. When the H.264 video bitstream is transformed into the MPEG-4 video bitstream, the conversions between H.264 block types and MPEG-4 block types are performed by minimizing distortion and the ${\times}4$ block-based motion vector mapping is performed. The proposed two transcoding methods run 4.14～5.1 times as fast as the cascaded transcoding methods in MPEG-4 encoder side, while the PSNR (peak-signal-to ratio) is slightly degrade with maximum 0.3dB.

• The KIPS Transactions:PartB
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• v.12B no.6 s.102
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• pp.637-646
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• 2005

Most of the multimedia contents for DBM services art provided as MPEG-2 bit streams. However, they have to be transcoded to H.264 bit streams for practical services because the standard video codec for DMB is H.264. The existing transcoder architecture is Cascaded Pixel-Domain Transcoding Architecture, which consists of the MPEG-2 dacoding phase and the H.264 encoding phase. This architecture can be easily implemented using MPEG-2 decoder and H.264 encoder without source modifying. However. It has disadvantages in transcoding time and DCT-mismatch problem. In this paper, we propose two kinds of transcoder architecture, DCT-OPEN and DCT-CLOSED, to complement the CPDT architecture. Although DCT-OPEN has lower PSNR than CPDT due to drift problem, it is efficient for real-time transcoding. On the contrary, the DCT-CLOSED architecture has the advantage of PSNR over CPDT at the cost of transcoding time.