• Journal of Electrical Engineering and Technology
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• 제9권2호
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• pp.489-500
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• 2014

This paper presents a simple modified unipolar carrier-based pulsewidth modulation (CB-PWM) strategy for the three-level neutral-point-clamped (NPC) voltage source inverter (VSI). Analytical expressions for the relationship between modulation reference signals and output voltages are derived. The proposed modulation technique for the three-level NPC VSI includes the maximum and minimum of the three-phase sinusoidal reference voltages with zero-sequence voltage injection concept. The proposed modified CB-PWM strategy incorporates a novel method that requires only of one triangular carrier wave for generate the gating pulses in three-level NPC VSI. It has the advantages of being simplifying the algorithm with no need of complex two/multi-carrier pulsewidth modulation or space vector modulation (SVM) and it's also simple to implement. The possibility of the proposed CB-PWM technique has been verified though computer simulation and experimental results.

• Journal of Power Electronics
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• 제14권3호
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• pp.531-540
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• 2014

A novel carrier-based PWM (CBPWM) strategy of a three-level NPC converter is proposed in this paper. The novel strategy can eliminate the low-frequency neutral point (NP) voltage oscillation under the entire modulation index and full power factor. The basic principle of the novel strategy is introduced. The internal modulation wave relationship between the novel CBPWM strategy and traditional SPWM strategy is also studied. All 64 modulation wave solutions of the CBPWM strategy are derived. Furthermore, the proposed CBPWM strategy is compared with traditional SPWM strategy regarding the output phase voltage THD characteristics, DC voltage utilization ratio, and device switching losses. Comparison results show that the proposed strategy does not cause NP voltage oscillation. As a result, no low-frequency harmonics occur on output line-to-line voltage and phase current. The novel strategy also has higher DC voltage utilization ratio (15.47% higher than that of SPWM strategy), whereas it causes larger device switching losses (4/3 times of SPWM strategy). The effectiveness of the proposed modulation strategy is verified by simulation and experiment results.

• Journal of Power Electronics
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• 제16권4호
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• pp.1336-1345
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• 2016

A modified space vector pulse width modulation (SVPWM) strategy based on vector space decomposition and its equivalent carrier-based PWM realization are proposed in this paper, which is suitable for six-phase asymmetrical dual stator induction machines (DSIMs). A DSIM is composed of two sets of symmetrical three-phase stator windings spatially shifted by 30 electrical degrees and a squirrel-cage type rotor. The proposed SVPWM technique can reduce torque ripples and suppress the harmonic currents flowing in the stator windings. Above all, the equivalent relationship between the proposed SVPWM technique and the carrier-based PWM technique has been demonstrated, which allows for easy implementation by a digital signal processor (DSP). Simulation and experimental results, carried out separately on a simulation system and a 3.0 kW DSIM prototype test bench, are presented and discussed.

• Journal of Electrical Engineering and Technology
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• 제12권2호
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• pp.738-750
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• 2017

In this paper, carrier-based pulse width modulation (CBPWM), space vector PWM (SVPWM) and reduced switching losses PWM (RSLPWM) for the three-level neutral point clamped (NPC) inverter are introduced. In the case of the neutral point (NP) potential (NPP) offset, an asymmetric disposition PWM (ASPDPWM) strategy is proposed, which can output PWM sequences correctly and suppress the lower order harmonics of the inverter effectively. An NPP balance strategy based on carrier based PWM (CBPWM) is analyzed. A hybrid modulation strategy combining RSLPWM and the NPP balance based on CBPWM is proposed, and hysteresis control is adopted to switch between the two modulation strategies. An experimental prototype of the three-level NPC inverter is built. The effectiveness of the hybrid modulation is verified with a resistance-inductance load and a permanent magnetic synchronous motor (PMSM) load, respectively. The experimental results show that reduced switching losses and an acceptable NPP can be effectively achieved in the hybrid modulation strategy.

• Journal of Electrical Engineering and Technology
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• 제11권2호
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• pp.393-404
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• 2016

In this paper, a carrier-based pulse with modulation (PWM) strategy for three-phase three-level inverter is dealt with, which can keep the common mode voltage constant with minimized switching frequency. The voltage gain and the switching frequency in overall operating ranges including overmodulation are investigated and the analytic equations are presented. Finally, the leakage current reduction effect is confirmed by carrying out simulation and experiment. It will be pointed out that the leakage current cannot be perfectly eliminated because of the dead time.

• Journal of Power Electronics
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• 제10권3호
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• pp.277-284
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• 2010

This paper presents a novel hybrid carrier based space vector modulation for cascaded multilevel inverters. The proposed technique inherits the properties of carrier based space vector modulation and the fundamental frequency modulation strategy. The main characteristic of this modulation are the reduction of power loss, and improved harmonic performance. The carrier based space vector modulation algorithm is implemented with a TMS320F2407 digital signal processor. A Xilinx Complex Programmable Logic Device is used to develop the hybrid PWM control algorithm and it is integrated with a digital signal processor for hybrid carrier based space vector PWM generation. The inverter offers less weighted total harmonic distortion and it operates with equal electrostatic and electromagnetic stress among the power devices. The feasibility of the proposed technique is verified by spectral analysis, simulation, and experimental results.

• 전력전자학회논문지
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• 제15권4호
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• pp.288-295
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• 2010

멀티레벨 인버터는 대용량 전력변환 분야의 요구를 만족하면서 파형왜곡을 감소시켜 전력품질 향상시킬 수 있으므로 근래에 상당히 주목받고 있다. 그런데 전압레벨이 증가함에 따라 복잡한 PWM 알고리즘을 구현하는데 FPGA가 적합하다. 본 논문에서는 FPGA로 5-레벨 다이오드 클램핑형 멀티레벨 인버터의 PWM 신호발생 기법을 제시한다. 유도전동기 제어용 DSP와 FPGA사이에 3상 기준전압 값을 안정되게 전송하는 기법을 제시한다. 32-비트 DSP와 cyclone-III FPGA를 사용한 실험 및 시뮬레이션을 통하여 반송신호 발생 방법으로 PWM 신호를 발생시키는 기법의 타당성을 검증한다.

• Journal of Power Electronics
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• 제17권6호
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• pp.1480-1489
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• 2017

In this study, a carrier-based pulse-width modulation (PWM) method for two-level voltage source inverters in the over-modulation region is proposed. Based on the superposition principle, the reference voltage vectors outside the linear modulation boundary are adjusted to relocate to the vector hexagon, while their fundamental magnitudes are retained. In accordance with the adjusted reference vector, the corresponding modulated waves are respectively deduced in over-modulation mode I and II to generate the gate signals of the power switches, guaranteeing the linearity of the fundamental output phase voltage in the over-modulation region. Moreover, due to the linear relationship between the voltage vector and the duty ratios, the complicated sector identification and holding angle calculation found in previous methods are avoided in the modulated wave synthesis, which provides great simplicity for the proposed carrier-based over-modulation strategy. Experimental results demonstrate the effectiveness and validity of the proposed method.

• 전기학회논문지
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• 제64권5호
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• pp.718-725
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• 2015

This paper proposes a novel level-shifted PWM (LS-PWM) strategy for fault tolerant cascaded multilevel inverter. Most proposed fault-tolerant operation methods in many of studies are based on a phase-shifted PWM (PS-PWM) method. To apply these methods to multilevel inverter systems using LS-PWM, two additional steps will be implemented. During the occurrence of a single-inverter-cell fault, the carrier bands scheme is reconfigured and modulation levels of inverter cells are reassigned in this proposed fault-tolerant operation. The proposed strategy performs balanced three-phase line-to-line voltages and line currents when a switching device fault occurs in a cascaded multilevel inverter using LS-PWM. Simulation and experimental results are included in the paper to verify the proposed method.

• 전력전자학회논문지
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• 제19권4호
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• pp.376-382
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• 2014

This paper proposes the pulse width modulation (PWM) control strategy for low-speed operation in the three-level neutral-point-clamped (NPC) inverters based on the bootstrap gate drive circuit. As a purpose of the cost reduction, several papers have paid attention to the bootstrap circuit applied to the three-level NPC inverter. However, the bootstrap gate driver IC cannot generate the gate signal to the IGBT for low-speed operation, because the bootstrap capacitor voltage decreases under the threshold level. For low-speed operation, the dipolar and partial-dipolar modulations can be the effective solution. However, these modulations have drawbacks in terms of the switching loss and THD. Therefore, this paper proposes the PWM control strategy to operate the inverter at low-speed and to minimize the switching loss and harmonics. The experimental results are presented to verify the validity on the proposed method.