• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.95-96
• /
• 2009

A fully depleted capacitorless 1-transistor dynamic random access memory (FD 1T-DRAM) based on a sSOI strained-silicon-on-insulator) wafer was investigated. The fabricated device showed excellent electrical characteristics of transistor such as low leakage current, low subthreshold swing, large on/off current ratio, and high electron mobility. The FD sSOI 1T-DRAM can be operated as memory device by the floating body effect when the substrate bias of -15 V is applied, and the FD sSOI 1T-DRAM showed large sensing margin and several milli seconds data retention time.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2010.06a
• /
• pp.346-346
• /
• 2010

A capacitorless one transistor dynamic random access memory (1T-DRAM) on silicon-germanium-on-insulator substrate was investigated. SGOI technology can make high effective mobility because of lattice mismatch between the Si channel and the SiGe buffer layer. To evaluate memory characteristics of 1T-DRAM, the floating body effect is generated by impact ionization (II) and gate induced drain leakage (GIDL) current. Compared with use of impact ionization current, the use of GIDL current leads to low power consumption and larger sense margin.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.28 no.11
• /
• pp.84-92
• /
• 2014

In this paper, we propose a three-phase isolated electrolytic capacitorless charger available for quick charger. In the proposed charger, electrolytic capacitor in DC link is eliminated by direct conversion from AC input to DC output. Conventional chargers are two stage structure including AC-DC and DC-DC converters, but the proposed charger can be simplified into single stage converter by using a matrix converter. And the waveform of input currents is improved by giving the weighting factor to the duty ratio of auxiliary switches. In order to verify the effectiveness of the proposed charger, simulations are carried out and a 1.2kW charger was constructed and experimented.

• KIEE International Transactions on Electrophysics and Applications
• /
• v.3C no.3
• /
• pp.73-76
• /
• 2003

In modern EHV (Extra High Voltage) class GCBs (Gas Circuit Breakers), the interruption capability for SLF (Short Line Fault) is one of the most important aspects of performance required for GCBs. Up to now, the SLF interruption capability of EHV class GCBs was partially assisted by the adoption of capacitors able to decrease the dV/dt of the TRV (Transient Recovery Voltage), particularly the TRV on the line side. This paper describes the technique to increase the SLF interruption capability of EHV class GCBs as well as the procedure to develop capacitorless l70kV 50kA GCB.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.11a
• /
• pp.35-35
• /
• 2009

Capacitorless one transistor dynamic random access memory (1T-DRAM) cells were fabricated on the fully depleted strained-silicon-on-insulator (FD sSOI) and the effects of silicon back interface state on buried oxide (BOX) layer on the memory properties were evaluated. As a result, the fabricated 1T-DRAM cells showed superior electrical characteristics and a large sensing current margin (${\Delta}I_s$) between "1" state and "0" state. The back interface of SOI based capacitorless 1T-DRAM memory cell plays an important role on the memory performance. As the back interface properties were degraded by increase rapid thermal annealing (RTA) process, the performance of 1T-DRAM was also degraded. On the other hand, the properties of back interface and the performance of 1T-DRAM were considerably improved by post RTA annealing process at $450^{\circ}C$ for 30 min in a 2% $H_2/N_2$ ambient.

• Proceedings of the KIPE Conference
• /
• 2008.10a
• /
• pp.178-180
• /
• 2008

직류단 전원(DC link)에 대용량의 전해 캐패시터(Electrolytic capacitor)를 사용하지 않는 전해 캐패시터리스(Electrolytic-Capacitorless) 인버터는 기존의 인버터에 비해서 가격, 부피 면에서 장점을 갖는다. 하지만 인버터의 용량이 커질수록 입력 저역 통과 필터(Low Pass Filter : LPF)와 주기적인 맥동을 가지는 직류단 전원의 영향을 받는다. 본 논문에서는 75[kW]급 캐패시터리스 인버터를 개발하여 이러한 영향을 억제할 수 있는 방법을 제시하고, 실험 결과를 통하여 개발한 인버터의 타당성을 검증한다.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.479-480
• /
• 2006

• Journal of IKEEE
• /
• v.19 no.4
• /
• pp.506-513
• /
• 2015

In this paper, an output-capacitorless, low-dropout (LDO) regulator is designed, which consumes $4.5{\mu}A$ quiescent current. Proposed LDO regulator is realized using two amplifier for good load regulation and fast response time, which provide high gain, high bandwidth, and high slew rate. In addition, a one-shot current boosting circuit is added for current control to charge and discharge the parasitic capacitance at the pass transistor gate. As a result, response time is improved during load-current transition. The designed circuit is implemented through a $0.11-{\mu}m$ CMOS process. We experimentally verify output voltage fluctuation of 260mV and recovery time of $0.8{\mu}s$ at maximum load current 200mA.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2009.08a
• /
• pp.212-212
• /
• 2009

• Proceedings of the KIEE Conference
• /
• 2008.07a
• /
• pp.888-889
• /
• 2008

본 논문은 직류단 전원(DC link)에 대용량의 전해 캐패시터(Electrolytic capacitor)를 사용하지 않는 전해 캐패시터리스 (Electrolytic-Capacitorless) 인버터의 입력 전류와 직류단 전원 공진(resonance) 억제에 대한 것이다. 직류단 전원의 순시적인 에너지원으로 사용되는 전해 캐패시터를 사용하지 않는 캐패시터리스 인버터는 기존의 인버터에 비해서 가격, 부피 면에서 장점을 가지지만, 직류단 전원의 캐패시터 용량이 작아서 부하 단 스위칭의 영향이 입력 전류에 직접적으로 나타나게 된다. 이에 따라서 캐패시터리스 인버터는 필연적으로 입력 단에 저역 통과 필터(Low Pass Filter : LPF)가 필요하다. 입력 단의 필터는 간단한 구조와 가격적 측면을 고려하여 LC 필터가 주로 사용되는데, LC필터는 직류단 전류에 의한 공진의 원인이 된다. 본 논문에서는 캐패시터리스 인버터의 입력 필터의 영향을 분석하여 입력 전류와 직류단 전압의 공진을 억제 할 수 있는 방법을 제시하고, 실험 결과를 통하여 제안된 방법의 유효성을 확인한다.