• 전기학회논문지
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• 제58권4호
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• pp.763-769
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• 2009

A series voltage compensation(SVC) system is a power-electronics controller that can protect sensitive loads from disturbance in the supply system. Especially, voltage sags are considered the dominant disturbances affecting the power quality. This paper dealt with a system of off-line type voltage sag compensation by using a bi-directional DC/DC converter of environmentally friendly ultra-capacitor. This capacitor is attached to the DC link of SVC through the high-efficiency DC/DC converter in order to compensate the DC link voltage drop during short-term power interruption as voltage sags. Therefore, in this paper, a DC/DC converter to control high-efficiency energy of ultra-capacitor and voltage sag detection algorithm of off-line type SVC systems are newly introduced. According to the results of experimental of prototype system, it is verified that the proposed system has effectiveness of voltage sag compensation using an ultra-capacitor.

• 전기학회논문지
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• 제60권2호
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• pp.315-319
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• 2011

A switched-capacitor cyclic DAC scheme with mismatch compensation of capacitors is designed. In cyclic DAC, a little error between two capacitors is accumulated every cycle. As a result, the accumulated error influences the final analog output which is wrong data. Therefore, a mismatch compensation technique was proposed and the error can be effectively reduced, which alleviates the matching requirement. In order to verify the operation of the proposed DAC, an 8-bit switched-capacitor cyclic DAC is designed through HSPICE simulation and implemented through magna 0.18um standard CMOS process.

• Journal of Power Electronics
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• 제16권4호
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• pp.1621-1628
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• 2016

Experiencing power declines when the secondary coil is at the middle position between two primary coils is a serious problem in segmented on-road charging systems with a single energized segmented primary coil. In this paper, the topological transformation of a primary circuit and a hierarchical compensation capacitor control are proposed. Firstly, the corresponding compensation capacitors and receiving powers of different primary structures are deduced under the condition of a fixed frequency. Then the receiving power characteristics as a function of the position variations in systems with a single energized segmented primary coil and those with double segmented primary coils are analyzed comparatively. A topological transformation of the primary circuit and hierarchical compensation capacitor control are further introduced to solve the foregoing problem. Finally, an experimental prototype with the proposed topological transformation and hierarchical compensation capacitor control is carried out. Measured results show that the receiving power is a lot more stable in the movement of the secondary coil. It is a remarkable fact that the receiving power rises from 10.8W to 19.2W at the middle position between the two primary coils. The experimental are in agreement with the theoretical analysis.

• 전기학회논문지P
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• 제58권2호
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• pp.101-107
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• 2009

This paper deal with development of on-line type voltage sag compensation system using supercapacitor EDLC to solve the voltage sag problems which are considered to be dominant disturbances affecting the power quality. With the wide use of semiconductor devices in electrical equipment, modem-type loads are becoming increasingly sensitive to the voltage sags and the disturbances prove to be costly to industries. Supercapacitor EDLC is employed to compensate dynamically for the voltage sag of system with sensitive loads. This capacitor has higher energy density than the electrolytic capacitor. Also, this capacitor has a lot of advantage such as no maintenance, longer life cycle and faster charge-discharge time than the battery system. Therefore, in this paper, the energy design scheme of supercapacitor and the configuration technique of on-line type voltage sag compensation systems are newly introduced. According to the results of experimental of prototype 5[kVA] system, it is verified that the developed system has effectiveness of voltage sag compensation by using a supercapacitor EDLC.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.537-538
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• 2008

A step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in 0.18um CMOS standard process. In an effort to improve low load efficiency, this paper proposes the PFM (Pulse Frequency modulation) voltage mode 1MHz switching frequency step-down DC-DC converter with on-chip compensation. Capacitor multiplier method can minimize error amplifier compensation block size by 20%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87% for the output voltage of 1.8V (input voltage : 3.3V), maximum load current 500mA, and 0.14% output ripple voltage. The total core chip area is $mm^2$.

• Journal of Power Electronics
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• 제16권5호
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• pp.1928-1938
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• 2016

The three-phase four-wire shunt active power filter (APF) is an effective method to solve the harmonic problem in three-phase four-wire power systems. In addition, it has two possible topologies, a four-leg inverter and a three-leg inverter with a split-capacitor. There are some studies investigating DC-link voltage control in three-phase four-wire APFs. However, when compared to the four-leg inverter topology, maintaining the balance between the DC-link upper and lower capacitor voltages becomes a unique problem in the three-leg inverter with a split-capacitor topology, and previous studies seldom pay attention to this fact. In this paper, the influence of the balance between the two DC-link voltages on the compensation performance, and the influence of the voltage balance controller on the compensation performance, are analyzed. To achieve the balance between the two DC-link capacitor voltages, and to avoid the adverse effect the voltage balance controller has on the APF compensation performance, a new DC-link voltage balance control strategy for the three-phase four-wire split-capacitor APF is proposed. Representative simulation and experimental results are presented to verify the analysis and the proposed DC-link voltage balance control strategy.

• 한국통신학회논문지
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• 제34권7A호
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• pp.568-573
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• 2009

본 논문에서 0.13um CMOS 공정으로 설계된 배터리 기반 휴대용 통신 시스템 구동용의 온칩 시동회로를 갖는 스텝다운 CMOS DC-DC 변환기를 제안하였다. 1MHz의 스위칭 주파수를 기반으로 설계된 벅 변환기에는 온칩 시동회로와 커패시터 멀티플라이어 기법을 이용한 보상회로를 포함시켰다. 칩 측정 결과 2.5V ${\sim}$3.3V의 입력 전압을 1.2V로 강압시키는데 최대 87.2%의 효율을 갖는다. 최대 부하 전류, 출력 전류 리플 및 전압 리플은 각각 500mA, 25mA, 24mV 이다.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2009년도 춘계학술대회 논문집
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• pp.879-891
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• 2009

Impedance of rails is increased by the magnetic coupling between rails and reinforcing bars in the concrete slab track. Currently, the current of track circuit has been compensated by installing the compensation capacitors on track circuit because of increasing the impedance of rails. In case of a rapid transit railway, the compensation capacitors are installed every 20[m] to compensate the current of track circuit in the concrete slab track. Because the interval of one block for a rapid transit railway is as long as 1500[m], the compensation capacitors are installed about the number of 70$\sim$75 on track circuit. However, in case the compensation capacitors are broken over the number of three, it is a problem that the amplitude of current is under standard amplitude of current which is 0.8[A]. In this paper, it was suggested installing a compensation capacitor by using resonance phenomenon on the concrete slab track. We represent the electrical model of track circuit and the four terminal network, calculate the parameters demanded for the electrical model in the concrete slab track. Also, we computed the position and capacitance of the compensation capacitor about 2040[Hz], 2400[Hz], 2760[Hz], 3120[Hz] which currently is the track circuit frequency in the Gyeongbu rapid transit railway and demonstrated the validity of it, using the Matlab and PSpice program.

• Transactions on Electrical and Electronic Materials
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• 제17권3호
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• pp.172-177
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• 2016

Miller feedback compensation is introduced in a low dropout regulator (LDO) in order to obtain a capacitor-free regulator and improve the fast transient response. The conventional LDO has a limited bandwidth because of the large-size output capacitor and parasitic gate capacitance in the power MOSFET. In order to obtain a stable frequency response without the output capacitor, LDO is designed with resistor-capacitor (R-C) compensation and this is achieved with a connection between the gain-stage and the power MOS. An R-C compensator is suggested to provide a pole and zero to improve the stability. The proposed LDO is designed with the 0.35 μm CMOS process. Simulation testing shows that the phase margin in the Bode plot indicates a stable response, which is over 100^o. In the load regulation, the transient time is within 55 μs when the load current changes from 0.1 to 1 mA.

• 전력전자학회논문지
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• 제9권4호
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• pp.381-389
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• 2004

본 논문에서는 입력단 커패시터를 제거한 인버터의 제어에 아날로그 적분기를 이용한 새로운 비선형 제어 기법인 순시보상형 PWM 제어회로를 적용하고 있다. 비선형 순시보상형 PWM 제어기는 순시 입력전압의 변동에 대한 보상과 제어기준값에 대한 추종이 스위칭 한 주기 내에서 이루어지는 다이나믹하고 강인한 응답성을 가지고 있으며, 아날로그 소자를 사용하고 있어 제어회로가 간단하면, 인버터 입력 맥동전압을 보상함으로 대형의 평활용 커패시터가 필요치 않아서 소형, 저가형으로 부피가 적은 인버터를 제작 할 수 있다는 장점을 가지고 있다. 이러한 장점을 가지고 있는 순시보상형 PWM 제어 인버터를 기존의 VVVF 제어형 전동기 인버터 시스템을 대치하여 저가이고 소형의 인버터 시스템으로 제안하고 실험을 통하여 우수한 동작특성을 확인하고 있다.