• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.12
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• pp.1016-1022
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• 2001

This study presents the microstructure-electrical property relationship of reactive-sputtered Ta$_2$O$_{5}$ MIM capacitor structure processed by annealing in a vacuum and $O_2$ ambience. A microstructural investigation showed the existence of amorphous phase in as-deposited condition and the formation of preferentially oriented-Ta$_2$O$_{5}$ in $700^{\circ}C$ annealing. On annealing under the $O_2$ atmosphere, the Ta$_2$O$_{5}$ film exhibited the trend of its composition\`s approaching to stoichiometry from off-stoichiometry, analyzed by EPMA, the leakage current decrease and the enhanced temperature-capacitance characteristic stability. In the case of low temperature vacuum-annealing treatment, the leakage current behavior was stable irrespective of applied electric field. In the high temperature-annealed film at a vacuum condition, the electrical properties was observed to deteriorate. The results state that in Ta$_2$O$_{5}$ film annealed at $O_2$ atmosphere, gives rise to improvement of electrical characteristics in the capacitor were improved by reducing oxygen-vacancy and dandling Ta-O bond.-O bond.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.15-21
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• 2013

In this paper, a MEMS tunable capacitor was successfully designed and fabricated using an aluminum nitride film and a gold suspended membrane with two air gap structure for commercial RF applications. Unlike conventional two-parallel-plate tunable capacitors, the proposed tunable capacitor consists of one air suspended top electrode and two fixed bottom electrodes. One fixed and the top movable electrodes form a variable capacitor, while the other one provides necessary electrostatic actuation. The fabricated tunable capacitor exhibited a capacitance tuning range of 375% at 2 GHz, exceeding the theoretical limit of conventional two-parallel-plate tunable capacitors. In case of the contact state, the maximal quality factor was approximately 25 at 1.5 GHz. The developed fabrication process is also compatible with the existing standard IC (integrated circuit) technology, which makes it suitable for on chip intelligent transceivers and radios.

• Journal of Electrical Engineering and Technology
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• v.11 no.1
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• pp.100-108
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• 2016

This paper presents a simple high efficiency full-bridge DC-DC converter using a series resonant capacitor. The proposed converter achieves the zero voltage switching of the primary switches under a wide range of load conditions and reduces the high circulating current in the freewheeling mode using the leakage resonant inductance and the series resonant capacitor. Thus, the proposed converter overcomes the drawbacks of the conventional full-bridge DC-DC converter and improves its overall system efficiency. Its structure is simplified by using the leakage inductance of the transformer as the resonant inductance and omitting the DC output filter inductance. Also it can operate over a wide range of input voltages. In this paper, the operational principle, analysis and design example are described in detail. Finally, the experimental results from a 650W (24V/27A) prototype are demonstrated to confirm the operation, validity and features of the proposed converter.

• Journal of Information Display
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• v.9 no.2
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• pp.9-13
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• 2008

A novel push-pull voltage converter structure, using a switched capacitor type voltage doubler, is proposed. The circuit is constructed with a two-stage push-pull voltage doubler that has a stable operation with small output ripple. The two-stage voltage doubler creates the output voltage 4Vdd. The high clock signal is cross-coupled to the input of the second stage with the opposite phase to reduce two switching transistors and capacitors. Simulation results verify that even with a reduced number of transistor and capacitor, there is no circuit performance loss. Adding one capacitor and two switching transistors the circuit can be changed to eight times of Vdd maker.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.119-119
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• 2008

The electrical characteristics of Metal-Ferroelectric-Nitride-Oxide-Silicon (MFNOS) structure is studied and compared to the conventional Silicon-Oixde-Nitride-Oxide-Silicon (SONOS) capacitor. The ferroelectric blocking layer is SrBiNbO (SBN with Sr/Bi ratio 1-x/2+x) with the thickness of 200 nm and is fabricated by the RF sputter. The memory windows of MFNOS and SONOS capacitors with sweep voltage from +10 V to -10 V are 6.9 V and 5.9 V, respectively. The effect of ferroelectric blocking layer and charge trapping on the memory window was discussed. The retention of MFNOS capacitor also shows the 10-years and longer retention time than that of the SONOS capacitor. The better retention properties of the MFNOS capacitor may be attributed to the charge holding effect by the polarization of ferroelectric layer.

• Journal of Power Electronics
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• v.17 no.5
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• pp.1195-1202
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• 2017

This paper presents a novel topology named a modified capacitor-assisted Z-source inverter (MCA-ZSI) based on the traditional ZSI. The impedance network of the proposed MCA-ZSI consists of two symmetrical cells coupled with two capacitors with an X-shape structure, and each cell has two inductors, two capacitors, and one diode. Compared with other topologies based on switched ZSI with the same number of components used at impedance network, the proposed topology provides higher boost ability, lower voltage stress across inverter switching devices, and lower capacitor voltage stress. The improved performances of the proposed topology are demonstrated in the simulation and experimental results.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.412-415
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• 2003

[ $Si_3N_4$ ] thin film is the good material to fabricate the capacitors at MMIC processes. Normally, $Si_3N_4$ thin films is used to dielectric in the MIM capacitor and film thickness is $2000\;{\AA}$. Insulator(or dielectric) was deposited by PECVD at our MIM structure with air bridge which connect between top metal and contact pad. We optimized PECVD process to fabricate the good capacitors which can be applied at the true MMIC. The thickness of our $Si_3N_4$ thin films was $1000\;{\AA}$ shallower than $2000\;{\AA}$, and their breakdown voltages were above 70V.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.25 no.8
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• pp.20-29
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• 2011

This paper presents an improved phase-shift pulse-width modulation (PWM) full-bridge converter using a blocking capacitor. As the proposed converter reduces the circulation energy by inserting only one series blocking capacitor at the primary side of the conventional phase-shift PWM full-bridge converter structure, it improves the operation characteristics of the conventional converter. In this paper, first, the operation of conventional phase-shift PWM full-bridge converter is roughly reviewed, and then the operational principle of the proposed converter is classified and explained by each mode. After that, a prototype design example based on the operational principle is shown. Then, the improved operation characteristics of the proposed converter are actually verified through the experimental results.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.250-250
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• 2007

In this paper, multilayer piezoelectric transformer for high power is presented. This piezoelectric transformer, with a multilayered construction in the thickness direction, was fabricated at the sintering temperature of $1055^{\circ}C$. The electrical properties of multilayer piezoelectric transformer as a function of Internal electrode structure, with same size, were investigated. Also, the multilayer piezoelectric transformer with different layer number of 5, 10, 15 layers, were investigated.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.38-39
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• 2006

In this paper, we describe a method of accurate modeling capacitor in Low Temperature Co-fired Ceramic(LTCC). We obtain building blocks that present characterization of test structure through partial element equivalent circuit (PEEC) method. The extracted model of building blocks can be used for predicting behaviors of capacitors with different geometries. This method can provide the good inspection of capacitor to device engineer.