• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2007년도 하계종합학술대회 논문집
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• pp.437-438
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• 2007

In this paper a embedded decoupling capacitor design with gap structure will be discussed. A novel structure is modeling and analization by High Frequency Structure Simulator (HFSS). Proposed capacitor have $2m{\times}2m$ in rectangular shape. The film thickness of copper/dielectric film/substrate is respectively 35um/20um/35um. A dielectric layer of BaTiO3/epoxy has the relative permittivity of 25. Compare of the planar decoupling capacitor, capacitance densities of this structure in the range of $55{\mu}F$/mm2 have been obtained with 50um gap while capacitance densities of planar structure $55{\mu}F$/mm2 in the same size. The frequency dependent behavior of capacitors is numerically extracted over a wide frequency bandwidth 500MHz-7GHz. The decoupling capacitor can work at high frequency band increasing the gap size.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권3호
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• pp.387-400
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• 2017

A new junction-splitting based SAR ADC with a redundant searching capacitor array structure in $0.13{\mu}m$ CMOS process to alleviate capacitor mismatch effects, is presented. The normalized average power has a factor of 0.35 to the conventional SAR ADC at 10-bit conversion accuracy. Statistical experiments show the number of missing codes resulting from the mismatch reduces by 95% for 3% unit-capacitor mismatch ratio, while keeping the conversion energy to that of the conventional JS capacitor array.

• 센서학회지
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• 제24권2호
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• pp.131-136
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• 2015

This paper presents a wide dynamic range complementary metal oxide semiconductor (CMOS) image sensor with column capacitor and feedback structure. The designed circuit has been fabricated by using $0.18{\mu}m$ 1-poly 6-metal standard CMOS technology. This sensor has dual mode operation using combination of active pixel sensor (APS) and passive pixel sensor (PPS) structure. The proposed pixel operates in the APS mode for high-sensitivity in normal light intensity, while it operates in the PPS mode for low-sensitivity in high light intensity. The proposed PPS structure is consisted of a conventional PPS with column capacitor and feedback structure. The capacitance of column capacitor is changed by controlling the reference voltage using feedback structure. By using the proposed structure, it is possible to store more electric charge, which results in a wider dynamic range. The simulation and measurement results demonstrate wide dynamic range feature of the proposed PPS.

• 한국항행학회논문지
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• 제25권1호
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• pp.90-95
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• 2021

본 논문에서는 chipless RFID (radio frequency identification) 태그용 고감도 소형 공진기의 설계 방법을 제안하였다. 제안된 고감도 소형 공진기는 기존의 전계-결합(ELC; electric field-coupled) 공진기에서 커패시터 모양의 스트립 구조 대신에 인터디지털-커패시터(IDC; interdigital-capacitor) 구조를 사용하였다. IDC 구조의 극판 길이가 기존의 커패시터 모양 구조 보다 더 길어 공진기의 등가 커패시턴스가 더 커지고, 이로 인해 레이다 단면적(RCS; radar cross section)의 공진 피크 주파수를 낮출 수 있다. 정사각형 루프의 길이와 스트립의 폭이 같은 두 공진기를 두께 0.8 mm의 RF-301 기판에 제작하였다. 실험 결과, ELC 공진기는 bistatic RCS의 공진 피크 주파수와 값은 4.305 GHz와 -30.39 dBsm이었다. 제안된 IDC 공진기의 경우 bistatic RCS의 공진 피크 주파수와 값은 3.295 GHz와 -36.91 dBsm이었다. 따라서 측정 공진 피크 주파수를 기준으로 공진기 크기가 23.5% 정도 소형화되었다.

• 대한전자공학회논문지TE
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• 제42권4호
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• pp.1-6
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• 2005

최근 저항이나 캐패시터와 같은 수동소자를 PCB의 내층에 제조하는 임베디드 패시브 기술이 고성능의 IT 제품을 제조하는데 사용되고 있다. 그런데 임베디드 캐패시터는 정전용량 밀도가 낮아 회로소자로서의 전반적인 응용에 한계가 있다. 본 논문에서는 이러한 한계를 극복하기 위하여 wrinkle형의 전극과 유전체 층을 가진 새로운 임베디드 캐패시터를 제안하였다. FEM 기법을 사용하여 wrinkle형 임베디드 캐패시터의 정전용량 밀도를 평가하였다. Wrinkle형 임베디드 캐패시터는 기존의 평면형 임베디드 캐패시터에 비하여 25.6%$\sim$39.6% 정도 큰 정전용량 밀도를 나타내었다. 특히, thin film형 임베디드 캐패시터에 wrinkle 구조를 적용할 때 정전용량 밀도가 보다 많이 향상되었다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제51권5호
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• pp.185-190
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• 2002

Capacitor material utilized in the downsizing passive devices and dynamic random access memory(DRAM) requires the physical and electrical properties at given area such as capacitor thickness reduction, relative dielectric constant increase, low leakage current and thermal stability. Common capacitor materials, $SiO_2$, $Si_3N_4$, $SiO_2$/$Si_3N_4$,TaN and et al., used until recently have reached their physical limits in their application to several hundred angstrom scale capacitor. $Ta_2O_{5}$ is known to be a good alternative to the existing materials for the capacitor application because of its high dielectric constant (25 ~35), low leakage current and high breakdown strength. Despite the numerous investigations of $Ta_2O_{5}$ material, there have little been established the clear understanding of the annealing effect on capacitance characteristic and conduction mechanism, design and fabrication for $Ta_2O_{5}$ film capacitor. This study presents the structure-property relationship of reactive-sputtered $Ta_2O_{5}$ MIM capacitor structure processed by annealing in a vacuum. X-ray diffraction patterns skewed the existence of amorphous phase in as-deposited condition and the formation of preferentially oriented-$Ta_2O_{5}$ in 670, $700^{\circ}C$ annealing. On 670, $700^{\circ}C$ annealing under the vacuum, the leakage current decrease and the enhanced temperature-capacitance characteristic stability. and the leakage current behavior is stable irrespective of applied electric field. The results states that keeping $Ta_2O_{5}$ annealed at vacuum gives rise to improvement of electrical characteristics in the capacitor by reducing oxygen-vacancy and the broken bond between Ta and O.

• Journal of Power Electronics
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• 제18권4호
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• pp.1051-1066
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• 2018

This study presents a novel step-up switched capacitor multilevel inverter (SCMLI) structure. The proposed structure comprises 2 unequal DC voltage sources, 4 capacitors, and 14 unidirectional power switches. It can synthesize 21 output voltage levels. The important features of the proposed topology are its self-voltage boosting and inherent capacitor voltage balancing capabilities. Furthermore, a cascaded structure of the proposed SCMLI with an asymmetric DC voltage source configuration is presented. The proposed topology and its cascaded structure are compared with conventional and other recently developed topologies in terms of different aspects, such as the required components to produce a specific number of output voltage levels, the total standing voltage (TSV) and peak inverse voltage of the structure, and the maximum number of switches in the conducting path. Furthermore, a cost function is developed to verify the cost-effectiveness of the proposed topology with respect to other topologies. The TSV of the proposed topology is significantly lower than those of other topologies. Moreover, the developed topology is cost-effective compared with other topologies. A detailed operating principle, power loss analysis, and selection procedure for switched capacitors are presented for the proposed SCMLI structure. Extensive simulation and experimental studies of a 21-level inverter structure prove the effectiveness and merits of the proposed SCMLI.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.358-358
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• 2010

To improve the programming/erasing speed and leakage current of multiple dielectric stack tunnel barrier engineering (TBE) Non-volatile memory, We propose a new concept called staggered structure of TBE memory. In this study, We fabricated staggered structure capacitor on $Si_3N_4$ stacked HfAlO and measured C-V curve that can observe tunneling characteristic of this device as various annealing temperature compared with that of single layer $SiO_2$ capacitor.

• 반도체디스플레이기술학회지
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• 제20권4호
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• pp.167-170
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• 2021

Integrated passive device (IPD) technology has emerged with the need for 5G. In order to integrate and miniaturize capacitors inside IPD, various studies are actively performed using high-k materials and trench structures. In this paper, an EM(Electromagnetic) simulation study was performed by applying an oxide dielectric to the capacitors having a various trench type structures. Commercially available materials HfO₂, Al₂O₃, and Ta₂O₅ are applied to non, circle, trefoil, and quatrefoil type trench structures to confirm changes in each material or structure. As a result, the bigger the capacitor area and the higher dielectric constant of the oxide dielectric, the insertion loss tended to decrease.

• 한국전자파학회논문지
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• 제21권10호
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• pp.1103-1108
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• 2010

본 논문에서는 PIFA의 급전점과 단락점을 둘러싸는 급전 루프 내부에 커패시터 구조를 삽입하는 새로운 타입의 4중 대역(GSM900/DCS/PCS/W-CDMA) PIFA 설계를 제안한다. 커패시터의 삽입을 통해서 병렬 공진점인 2.01 GHz에서의 반사 계수 -2.73 dB를 -6.26 dB로 낮추는 효과를 얻을 수 있었다. 병렬 공진에서의 좋지 못한 방사 특성을 개선시킴으로써 고차 대역(DCS/PCS/W-CDMA)에서의 광대역 특성을 나타내었다.