• 제목/요약/키워드: Capacitive load

검색결과 74건 처리시간 0.031초

진상소전류시험용 Capacitor Load Bank 설계 (Design of Capacitor Load Bank for Capacitive Current Switching Tests)

  • 노창일;나대열;김선구;정흥수;김원만;이동준
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2002년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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    • pp.106-108
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    • 2002
  • Capacitive current switching test for circuit breaker and load breaker switch requires special attention because, after current interruption, the capacitive load contains an electrical charge and can cause dielectric restrike and re-ignition of the switching devices. therefore dielectric strength of capacitor load bank shall be able to withstand 4Vt (Vt : test voltage) and charging voltage discharged within 1 min. In this paper presents both characteristic of capacitive current switching tests and design of capacitor load bank.

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최소 지연시간을 갖는 CMOS buffer 회로의 설계 기법 (the Design Methodology of Minimum-delay CMOS Buffer Circuits)

  • 강인엽;송민규;이병호;김원찬
    • 대한전자공학회논문지
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    • 제25권5호
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    • pp.509-521
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    • 1988
  • In the designs of integrated circuits, the buffer circuits used for driving a large capacitive load from minimum-structured logic circuit outputs have important effects upon system throughputs. Therefore it is important to optimize the buffer circuits. In this paper, the principle of designing CMOS buffer circuits which have the minimum delay and drive the given capacitive load is discussed. That is, the effects of load capacitance upon rise time, fall time, and delay of the CMOS inverter and the effects of parasitic capacitances are finely analysed to calculate the requested minimum-delay CMOS buffer condition. This is different from the method by C.A. Mead et. al.[2.3.4.]which deals with passive-load-nMOS buffers. Large channel width MOS transistor stages are necessary to drive a large capacitive load. The effects of polysilicon gate resistances of such large stages upon delay are also analysed.And, the area of buffer circuits designed by the proposed method is smaller than that of buffer circuits designed by C.A. Mead's method.

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Efficient Simulation Method for Dielectric Barrier Discharge Load

  • Oleg, Kudryavtsev;Ahmed, Tarek;Nakaoka, Mutsuo
    • Journal of Power Electronics
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    • 제4권3호
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    • pp.188-196
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    • 2004
  • The dielectric barrier discharge is recognized as one of the efficient methods of ultraviolet light generation and ozone production. As well, it is widely utilized for gaseous wastes neutralization and other technological processes in industry. This electrochemical reaction is electrically equivalent to a nonlinear capacitive load that represents some difficulties for designing the power supply. Therefore, a conventional power supply is designed for a drastically simplified model of the load and generally is not optimal. This paper presents a fast simulation approach for the nonlinear capacitive model representation of the dielectric barrier discharge load lamp. The main idea of the proposed method is to use analytical solutions of the differential state equations for the load and find the unknown initial conditions for the steady state by an optimization method. The derived expressions for the analytical solutions are rather complicated, however they greatly reduce the calculation time, which make sense when a deeper analysis is performed. This paper introduces the proposed simulation method and gives some examples of its application such as estimation of the load equivalent parameters and load matching conditions.

Design Guidelines for a Capacitive Wireless Power Transfer System with Input/Output Matching Transformers

  • Choi, Sung-Jin
    • Journal of Electrical Engineering and Technology
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    • 제11권6호
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    • pp.1656-1663
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    • 2016
  • A capacitive wireless power transfer (C-WPT) system uses an electric field to transmit power through a physical isolation barrier which forms a pair of ac link capacitors between the metal plates. However, the physical dimension and low dielectric constant of the interface medium severely limit the effective link capacitance to a level comparable to the main switch output capacitance of the transmitting circuit, which thus narrows the soft-switching range in the light load condition. Moreover, by fundamental limit analysis, it can be proved that such a low link capacitance increases operating frequency and capacitor voltage stress in the full load condition. In order to handle these problems, this paper investigates optimal design of double matching transformer networks for C-WPT. Using mathematical analysis with fundamental harmonic approximation, a design guideline is presented to avoid unnecessarily high frequency operation, to suppress the voltage stress on the link capacitors, and to achieve wide ZVS range even with low link capacitance. Simulation and hardware implementation are performed on a 5-W prototype system equipped with a 256-pF link capacitance and a 200-pF switch output capacitance. Results show that the proposed scheme ensures zero-voltage-switching from full load to 10% load, and the switching frequency and the link capacitor voltage stress are kept below 250 kHz and 452 V, respectively, in the full load condition.

High Efficiency Alternating Current Driver for Capacitive Loads Using a Current-Balance Transformer

  • Baek, Jong-Bok;Cho, Bo-Hyung;Park, Joung-Hu
    • Journal of Power Electronics
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    • 제11권1호
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    • pp.97-104
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    • 2011
  • This paper proposes a new alternating current driving method for highly capacitive loads such as plasma display panels or piezoelectric actuators, etc. In the proposed scheme, a current balance transformer, which has two windings with the same turn-ratio, provides not only a resonance inductance for energy recovery but also a current balance among all of the switching devices of the driver for current stress reduction. The smaller conduction loss than conventional circuits occurs due to the dual conduction paths which are parallel each other in the current balance transformer. Also, the leakage inductances of the transformer are utilized as resonant inductors for energy recovery by the series resonance to the capacitive load. Furthermore, the resonance contributes to the small switching losses of the switching devices by soft-switching operation. To confirm the validity of the proposed circuit, prototype hardware with a 12-inch mercury-free flat fluorescent lamp is implemented. The experimental results are compared with a conventional energy-recovery circuit from the perspective of luminance performances.

표면 탄성파 장치를 이용한 용량성 부하의 신호처리 및 이를 이용한 초정밀 간극 측정 (Signal Processing of Capacitive Load and Gap Measurement with High Precision Using Surface Acoustic Wave Device)

  • 김재근;이택주;임수철;박노철;박영필;박경수
    • 한국소음진동공학회:학술대회논문집
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    • 한국소음진동공학회 2009년도 추계학술대회 논문집
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    • pp.376-380
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    • 2009
  • Surface acoustic wave (SAW) device is widely used as a bandpass filter, a chemical or physical sensor, and an actuator. In this paper, we propose the capacitive gap measurement system with high precision through the signal processing using SAW device. The research process is mainly composed of theoretical part and experimental part. In theoretical part, equivalent circuit model was used to simulate the SAW response by the change of capacitance. In experimental part, commercialized capacitor was used to see the SAW response by the change of load capacitance. After that, gap adjustment system was made physically and the SAW response by the change of gap which caused the capacitance change was measured. And resolution and stroke was decided comparing the signal change and basic measurement noise level.

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표면 탄성파 장치를 응용한 용량 성 변위센서의 설계 및 초정밀 간극 측정 (Design of Capacitive Displacement Sensor and Gap Measurement with High Precision Using Surface Acoustic Wave Device)

  • 김재근;이택주;임수철;박노철;박영필;박경수
    • 한국소음진동공학회논문집
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    • 제20권5호
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    • pp.437-443
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    • 2010
  • SAW device is widely used as band pass filters, chemical or physical sensors, and actuators. In this paper, we propose the capacitive gap measurement system with high precision using SAW device. The research process is mainly composed of theoretical and experimental part. In the theoretical part, equivalent circuit model was used to predict the SAW response by the change of load impedance. In the experimental part, commercialized capacitor was used to see the SAW response by the change of load capacitance to check the feasibility as a sensor unit. After that, experimental setup to measure and adjust the gap was made and the SAW response by the change of gap which caused the capacitance change was measured. Finally, resolution and stroke was decided compared with the signal change and basic measurement noise level.

반사 신호를 이용한 용량 성 센서의 신호처리 및 이를 이용한 초정밀 간극 측정 (Reflective Signal Based Signal Contioning of Capacitive Sensor and High Precision Gap Measurement)

  • 김재근;이택주;임수철;박경수;박노철;박영필;엄원석
    • 한국소음진동공학회:학술대회논문집
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    • 한국소음진동공학회 2010년도 추계학술대회 논문집
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    • pp.537-537
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    • 2010
  • High precision sensing is very important in various technologies. Especially, it is more important when it were applied to nano/micro meter level's sensing like AFM, storage, etc. And capacitive sensing is widely used method. To improve the measurement efficiency, many signal conditioners were studied and one of them was surface acoustic wave (SAW) device. SAW device is very widely used as a high frequency bandwidth filter. Due to the reflective characteristic of high frequency, the response of SAW device contains both propagative and reflective signal at the external impedance. In this paper, we used SAW device as signal conditioner of capacitive sensor. And high precision gap measurement was executed using capacitive load. Reference signal was reflective SAW response and the magnitude at the center frequency of SAW device by the change of impedance was checked. Finally, the attainable gap resolution was determined.

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Analysis of the Cross Talk Mechanism in Capacitive Micromachined Ultrasonic Transducers

  • Rho, Yongrae;Khuri-Yakub, Butrus T.
    • The Journal of the Acoustical Society of Korea
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    • 제20권3E호
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    • pp.31-37
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    • 2001
  • Finite element model of a cMUT is constructed using the commercial code ANSYS to analyze the cross talk mechanism. Calculation results of the complex load impedance seen by single capacitor cells are presented, and then followed by a calculation of the plane wave real load impedance seen by a parallel combination of many cells that are used to make a transducer. Cross talk between 1-D array elements is found to be due to two main sources: coupling through a Stoneley wave propagating at the transducer-water interface and coupling through Lamb waves propagating in the substrate. To reduce the cross talk level, the effect of various structural variations of the substrate are investigated, which include a change of its thickness and etched trenches or polymer walls between array elements.

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BICMOS 버퍼의 면적 최적 설계 (Area-Optimized Design of BICMOS Buffers)

  • 이희덕;한철희
    • 대한전자공학회논문지
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    • 제27권10호
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    • pp.89-95
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    • 1990
  • 동작 속도와 용량성 부하에 따른 최적소자크기를 결정할 수 있는 bipolar-CMOS 버퍼 모델을 제안한다. 면적 최적화를 위한 해석적 결과를 바이폴라의 고주입 효과 및 MOS의 챠넬 속도제한영역을 가정하여 구했다. BICMOS 버퍼의 면적은 용량성 부하에 거의 비례하는 에미터 길이와 챠넬 폭을 정함으로써 최적화된다는 것을 보이고, 회로 세뮬레이션 결과와 비교하여 확인하였다.

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