• Journal of Power Electronics
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• v.16 no.3
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• pp.849-860
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• 2016

The high-switching-frequency operation of power converters can achieve high power density through size reduction of passive components, such as capacitors, inductors, and transformers. However, a small-output capacitor that has small capacitance and low effective series resistance changes the small-signal model of the converter power stage. Such a capacitor can make the converter unstable by increasing the crossover frequency in the transfer function of the small-signal model. In this paper, the design and implementation of a high-frequency LLC resonant converter are presented to verify the power density enhancement achieved by decreasing the size of passive components. The effect of small output capacitance is analyzed for stability by using a proper small-signal model of the LLC resonant converter. Finally, proper design methods of a feedback compensator are proposed to obtain a sufficient phase margin in the Bode plot of the loop gain of the converter for stable operation at 500 kHz switching frequency. A theoretical approach using MATLAB, a simulation approach using PSIM, and experimental results are presented to show the validity of the proposed analysis and design methods with 100 and 500 kHz prototype converters.

• Journal of Power Electronics
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• v.17 no.5
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• pp.1298-1307
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• 2017

The constant on-time current-mode controlled (COT-CMC) switching dc-dc converter is stable, with no subharmonic oscillation in its current loop when a voltage ripple in its outer voltage loop is ignored. However, when its output capacitance is small or its feedback gain is high, subharmonic oscillation may occur in a COT-CMC buck converter with a proportional-integral (PI) compensator. To investigate the subharmonic instability of COT-CMC buck converters with a PI compensator, an accurate reduced-order asynchronous-switching map model of a COT-CMC buck converter with a PI compensator is established. Based on this, the instability behaviors caused by output capacitance and feedback gain are investigated. Furthermore, an approximate instability condition is obtained and design-oriented stability boundaries in different circuit parameter spaces are yielded. The analysis results show that the instability of COT-CMC buck converters with a PI compensator is mainly affected by the output capacitance, output capacitor equivalent series resistance (ESR), feedback gain, current-sensing gain and constant on-time. The study results of this paper are helpful for the circuit parameter design of COT-CMC switching dc-dc converters. Experimental results are provided to verify the analysis results.

• Journal of the Korean Institute of Telematics and Electronics
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• v.7 no.2
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• pp.33-42
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• 1970

This report is concerned with the fahrication with the falricationof silicon VVC diode by the double diffusion planer technique. At first, some design charts for VVC diode were derived by considering the voltage-capacitance relations, the critical field intensity at the metallurgical junction, and the cut-off frequency of the diode. These charts enables the fabrication engineers to design VVC diode easily without going into the sophisticated design theory. We started with a 2.5 ohm-cm n-type epitaxial silicon wafer. The phosphorous was diffused by POCl3 impurity source. Then boron diffusion followed make hyperabrupt p-n junction by BN source. The maximum to minimum capacitance ratio of the diode as a tuning diode for a TV tuner made in these experiments was 4:1. Measured electrical characteristics of the sample diodes showed in good agreement with the theoretical expectations. Slicing and polishing technique of the silicon wafer and diffusion technique of the impurity atoms, which were employed in our study, are also stated briefly in this report.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.12
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• pp.992-995
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• 2018

The wireless charging of body-embedded medical instruments and wireless power transfer to various inside dielectric-materials is still a future technology that has not yet been achieved. This paper proposes methods for controlling the capacitance of the resonators and installing air pockets on the top and bottom sides of the resonators for optimal design, which considered efficiency and resonant frequency in accordance with the electromagnetic characteristics of the dielectric medium. In future, the results of this research will be utilized as the basic research data to design and restore resonant frequency of resonators embedded in various dielectric environments.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.525-536
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• 2014

Recently, the first generation of mass production of FinFET-based microprocessors has begun, and scaling of FinFET transistors is ongoing. Traditional capacitance and resistance models cannot be applied to nonplanar-gate transistors like FinFETs. Although scaling of nanoscale FinFETs may alleviate electrostatic limitations, parasitic capacitances and resistances increase owing to the increasing proximity of the source/drain (S/D) region and metal contact. In this paper, we develop analytical models of parasitic components of FinFETs that employ the raised source/drain structure and metal contact. The accuracy of the proposed model is verified with the results of a 3-D field solver, Raphael. We also investigate the effects of layout changes on the parasitic components and the current-gain cutoff frequency ($f_T$). The optimal FinFET layout design for RF performance is predicted using the proposed analytical models. The proposed analytical model can be implemented as a compact model for accurate circuit simulations.

• Journal of Applied Reliability
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• v.12 no.2
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• pp.67-78
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• 2012

An electric double-layer capacitor(EDLC) is an electrochemical capacitor with relatively high energy density, typically hundreds of times greater than conventional electrolytic capacitors. EDLCs are widely used for energy storage rather than as general-purpose circuit components. They have a variety of commercial applications, notably in energy smoothing and momentary-load devices, and energy-storage and kinetic energy recovery system devices used in vehicles, etc. This paper presents an accelerated degradation test of an EDLC with rated voltage 2.7V, capacitance 100F, and usage temperature $-40^{\circ}C{\sim}65^{\circ}C$. The EDLCs are tested at $50^{\circ}C$, $60^{\circ}C$, and $70^{\circ}C$, respectively for 1,750hours, and their capacitances are measured at predetermined times by constant current discharge method. The failure times are predicted from their capacitance deterioration patterns, where the failure is defined as 30% capacitance decrease from the initial one. It is assumed that the lifetime distribution of EDLC follows Weibull and Arrhenius life-stress relationship holds. The life-stress relationship, acceleration factor, and $B_{10}$ life at design condition are estimated by analyzing the accelerated life test data.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.6
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• pp.1297-1303
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• 2003

This paper propose an advanced circuit for fingerprint sensor signal processing. We increased the voltage between ridge and valley by modifying the parasitic capacitance eliminating circuit of sensor plate. The analog comparator was designed for comparing the sensor signal voltage with the reference signal voltage. We also propose an effective isolation strategy for removing noise and signal coupling, ESD of each sensor pixel. The 128${\times}$l44 pixel fingerprint sensor circuit was designed and simulated, and the layout was performed.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.51 no.1
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• pp.23-28
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• 2002

In order to survey the radiation characteristics of pure line noise of unwanted noise from overhead high voltage AC transmission lines, a disk type gap noise generator was manufactured. Disk size which decides capacitance between the noise generator and earth was selected through preliminary indoor experiments and analysis by using surface charge method. The capacitance is one of principal parameters related to the injection of a proper noise current into lines. On the basis of the capacitance obtained from calculation, 5mm of space was given to the gap of the noise generator to be installed o test line and an aluminum disk of 60cm radius was made. The field experiments were performed with the noise generator hung on the Kochang 765 kV full scale test line. As the results, the useful data which can be used to analysis the radiation characteristics of noise from transmission lines were obtained. Those are the directivity of antenna toward the line, lateral profiles, frequency spectra, height pattern and so on.

• The Transactions of the Korea Information Processing Society
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• v.4 no.8
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• pp.2143-2151
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• 1997

As inter-wire spacing on a VLSI chip becomes smaller with the evolution of VLSI fabrication technology, coupling capacitance between adjacent wires is increasing rapidly over ground capacitance. Therefore, it becomes necessary to take into account the crosstalk caused mainly by coupling capacitance during the layout design of VLSI systems. This paper deals with layer assignment problem to minimize crosstalk in three layers gridded channel routing. The problem is formulated in 0/1 integer linear programming style. Upper bound for cost function is estimated for the fast termination. Experiment shows the effectiveness of our approach to minimize crosstalk.

• Journal of the Korean Society of Safety
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• v.8 no.4
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• pp.95-100
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• 1993

In power transistor switching circuit have shunt snubber(dv/dt limiting capacitor) and series snubber (di/dt limiting inductor). The shunt snubber is used to reduce the turn-off switching loss and the series snubber is used to reduce the turn-on switching loss. Design procedures are derived for selecting the capacitance, inductor and resistance to limit the peak voltage and current values. The action of snubber is analyzed and applied to the design for safety PWM inverter.