• Journal of Power Electronics
• /
• 제16권3호
• /
• pp.849-860
• /
• 2016

The high-switching-frequency operation of power converters can achieve high power density through size reduction of passive components, such as capacitors, inductors, and transformers. However, a small-output capacitor that has small capacitance and low effective series resistance changes the small-signal model of the converter power stage. Such a capacitor can make the converter unstable by increasing the crossover frequency in the transfer function of the small-signal model. In this paper, the design and implementation of a high-frequency LLC resonant converter are presented to verify the power density enhancement achieved by decreasing the size of passive components. The effect of small output capacitance is analyzed for stability by using a proper small-signal model of the LLC resonant converter. Finally, proper design methods of a feedback compensator are proposed to obtain a sufficient phase margin in the Bode plot of the loop gain of the converter for stable operation at 500 kHz switching frequency. A theoretical approach using MATLAB, a simulation approach using PSIM, and experimental results are presented to show the validity of the proposed analysis and design methods with 100 and 500 kHz prototype converters.

• Journal of Power Electronics
• /
• 제17권5호
• /
• pp.1298-1307
• /
• 2017

The constant on-time current-mode controlled (COT-CMC) switching dc-dc converter is stable, with no subharmonic oscillation in its current loop when a voltage ripple in its outer voltage loop is ignored. However, when its output capacitance is small or its feedback gain is high, subharmonic oscillation may occur in a COT-CMC buck converter with a proportional-integral (PI) compensator. To investigate the subharmonic instability of COT-CMC buck converters with a PI compensator, an accurate reduced-order asynchronous-switching map model of a COT-CMC buck converter with a PI compensator is established. Based on this, the instability behaviors caused by output capacitance and feedback gain are investigated. Furthermore, an approximate instability condition is obtained and design-oriented stability boundaries in different circuit parameter spaces are yielded. The analysis results show that the instability of COT-CMC buck converters with a PI compensator is mainly affected by the output capacitance, output capacitor equivalent series resistance (ESR), feedback gain, current-sensing gain and constant on-time. The study results of this paper are helpful for the circuit parameter design of COT-CMC switching dc-dc converters. Experimental results are provided to verify the analysis results.

• 대한전자공학회논문지
• /
• 제7권2호
• /
• pp.33-42
• /
• 1970

액상과 고상의 불순물원을 사용한 이중확산법을 이용하여 초분수형 p-n 접합 VVC다이오드를 열작하고 그 특성을 측정하였다. 먼저 접합부근의 불순물분포를 지수난수로 근사시키고 여기에서 부터 유도되는 인가전압대 접태용총번계, 접합부에서의 섬계로계강도, 규재주파수 등을 고려하여 WC 다이오드외 새로운 담계수법을 위시하였다. 이 설계도표는 원하는 특성의 VVC다이오드를 번표와에서 나접 설계 할수있으므로 매우 사리하다. VVC다이오드는 2.5ohnm-cm의 n형, 실리콘박편위에 도너불순물 POCl3를 사용하여 선을 확정시키고, 다시 억셉터 불순물 BN을 사용하여 붕소를 확산시켜서, 접합깊이 2미크론에 초단계형접합을 만드므로서 제작하였다. 본연구에서 텔레비젼 수상기튜너용으로 시작한 다이오드의 최대용량대 총소용량의 비는 4:1이였고 그외의 전기적 제 특성도 이론적으로 설계한 값들과 거의 합치된 결과를 얻었다. 한편 이때의 실리콘 박편의 제작법과 확산기술에 관하여 간단히 기술하였다.

• 한국전자파학회논문지
• /
• 제29권12호
• /
• pp.992-995
• /
• 2018

본 논문에서는 향후 인체 내장형 의료기기의 무선충전 및 지금까지는 발생하지 않은 다양한 유전체 내부로의 무선전력전송 시 유전체 매질의 전자기적 특성에 따른 효율 및 공진주파수 변화에 대한 공진기의 최적화 설계를 위해 공진기의 정전용량(capacitance)을 조정하는 방법과 공진기의 전후 표면에 공기층(air pocket) 설치 방법을 제안하였다. 본 연구결과는 추후 공진기를 둘러싼 다양한 유전체 환경에 대한 공진주파수의 설계 및 복원에 대한 기초 연구 자료로 활용될 수 있다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제14권5호
• /
• pp.525-536
• /
• 2014

Recently, the first generation of mass production of FinFET-based microprocessors has begun, and scaling of FinFET transistors is ongoing. Traditional capacitance and resistance models cannot be applied to nonplanar-gate transistors like FinFETs. Although scaling of nanoscale FinFETs may alleviate electrostatic limitations, parasitic capacitances and resistances increase owing to the increasing proximity of the source/drain (S/D) region and metal contact. In this paper, we develop analytical models of parasitic components of FinFETs that employ the raised source/drain structure and metal contact. The accuracy of the proposed model is verified with the results of a 3-D field solver, Raphael. We also investigate the effects of layout changes on the parasitic components and the current-gain cutoff frequency ($f_T$). The optimal FinFET layout design for RF performance is predicted using the proposed analytical models. The proposed analytical model can be implemented as a compact model for accurate circuit simulations.

• 한국신뢰성학회지:신뢰성응용연구
• /
• 제12권2호
• /
• pp.67-78
• /
• 2012

An electric double-layer capacitor(EDLC) is an electrochemical capacitor with relatively high energy density, typically hundreds of times greater than conventional electrolytic capacitors. EDLCs are widely used for energy storage rather than as general-purpose circuit components. They have a variety of commercial applications, notably in energy smoothing and momentary-load devices, and energy-storage and kinetic energy recovery system devices used in vehicles, etc. This paper presents an accelerated degradation test of an EDLC with rated voltage 2.7V, capacitance 100F, and usage temperature $-40^{\circ}C{\sim}65^{\circ}C$. The EDLCs are tested at $50^{\circ}C$, $60^{\circ}C$, and $70^{\circ}C$, respectively for 1,750hours, and their capacitances are measured at predetermined times by constant current discharge method. The failure times are predicted from their capacitance deterioration patterns, where the failure is defined as 30% capacitance decrease from the initial one. It is assumed that the lifetime distribution of EDLC follows Weibull and Arrhenius life-stress relationship holds. The life-stress relationship, acceleration factor, and $B_{10}$ life at design condition are estimated by analyzing the accelerated life test data.

• 한국정보통신학회논문지
• /
• 제7권6호
• /
• pp.1297-1303
• /
• 2003

반도체 방식의 capacitive type 지문인식센서의 신호처리를 위한 개선된 회로를 설계하였다. 최 상위 sensor plate가 지문의 굴곡을 감지한 capacitance의 변화를 전압의 신호로 전환하기위해서 charge-sharing 방식의 회로를 적용하였다. 지문센서 감도저하의 가장 큰 원인인 sensor plate에 존재하는 parasitic capacitance를 최소화하고 ridge와 valley 사이의 전압차를 향상시키기 위하여 기존과는 다른 아날로그버퍼회로를 설계하였다. 센서전압과 기준전압 신호를 비교하기 위해서 비교기를 설계하였으며, 센서어레이의 수직, 수평간 isolation 대책을 통하여 ESD 및 노이즈방지를 위한 설계를 제안하였다. 제안된 신호처리회로는 128${\times}$l44 pixel 규모의 회로로 구현되었다. 본 설계회로는 향후 생체인식을 이용한 정보보호용 지문인식 시스템에 응용될 수 있으리라본다.

• 대한전기학회논문지:전력기술부문A
• /
• 제51권1호
• /
• pp.23-28
• /
• 2002

In order to survey the radiation characteristics of pure line noise of unwanted noise from overhead high voltage AC transmission lines, a disk type gap noise generator was manufactured. Disk size which decides capacitance between the noise generator and earth was selected through preliminary indoor experiments and analysis by using surface charge method. The capacitance is one of principal parameters related to the injection of a proper noise current into lines. On the basis of the capacitance obtained from calculation, 5mm of space was given to the gap of the noise generator to be installed o test line and an aluminum disk of 60cm radius was made. The field experiments were performed with the noise generator hung on the Kochang 765 kV full scale test line. As the results, the useful data which can be used to analysis the radiation characteristics of noise from transmission lines were obtained. Those are the directivity of antenna toward the line, lateral profiles, frequency spectra, height pattern and so on.

• 한국정보처리학회논문지
• /
• 제4권8호
• /
• pp.2143-2151
• /
• 1997

대규모 집적회로의 공정 기술의 발달로 전선 간의 간격이 가까와 짐에 따라서, 전선 간에 발생하는 결합 캐패시턴스가 접지 캐패시턴스에 비하여 급격히 증가하게 되었다. 그에 따라, 레이아웃의 설계과정에서 결합 캐패시턴스로 유발되는 혼신을 중요한 요인으로 고려할 필요가 있게 되었다. 본 논문에서는 3개 이상의 배선 층을 사용하는 배선 영역, 특히 채널 배선 영역에서 혼신을 최소화시킬 수 있는 배선 층 할당 방법을 다룬다. 제안된 방법은 배선 층 할당 문제를 0/1 정수 선형 프로그래밍 문제로 형식화하여 해결하는 것이다. 또한, 비용 함수에 대한 상한을 추정함으로써 효율을 향상시키는 방법을 제안한다. 실험을 통하여 제안된 방법이 혼신을 효과적으로 개선함을 보인다.

• 한국안전학회지
• /
• 제8권4호
• /
• pp.95-100
• /
• 1993

In power transistor switching circuit have shunt snubber(dv/dt limiting capacitor) and series snubber (di/dt limiting inductor). The shunt snubber is used to reduce the turn-off switching loss and the series snubber is used to reduce the turn-on switching loss. Design procedures are derived for selecting the capacitance, inductor and resistance to limit the peak voltage and current values. The action of snubber is analyzed and applied to the design for safety PWM inverter.