• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(1)
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• pp.393-396
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• 2000

Repeater Duplexer of 800MHz band consists of 4pole transmitter band pass filter, receiver band pass filter and branch circuit. Circuit parameter of Duplexer such as coupled capacitance of equivalent circuit was drawn out and used to coupled line characteristics impedance (Zoo, Zoe) that satisfied resonator condition and attenuation condition. Simulation was carried out by the ADS(Advanced Design System) were obtained good attenuation characteristics (869~894MHz： 65㏈(Min.),824~349MHz： 65㏈(Min.)

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 추계 기술심포지움
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• pp.61-66
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• 2001

In this research, the design parameters of embedded capacitors are extracted by modeling and fabrication. The traditional library of capactor has a few problems in applying the circuit. Its capacitance is discrete, so target values in any circuit often can't be obtained in library, To solve this problem, the characteristics of capacitors are detected in the variation with the shape and structure, and then the capacitors with the expected reactance value at target frequency are obtained, In this procedure, 3-dimensional structure simulation is performed to predict the characteiristics of capacitors.

• ETRI Journal
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• 제28권4호
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• pp.506-508
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• 2006

A frequency selective surface (FSS), whose unit cell consists of a ternary tree loop loaded with a modified tripole, is proposed to block multiple frequency bands. Target frequency bands correspond to Korean personal communication services, cellular mobile communication, and 2.4 GHz industrial, scientific, and medical bands. Through the adjustment of inter-element and inter-unit cell gaps, and adjustment of the length of elements, we present an FSS design method that makes the precise tuning of multiple resonance frequencies possible. Additionally, to verify the validity of our approach, simulation results obtained from a commercial software tool and experimental data are also presented.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.369-372
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• 1999

In this paper, we propose a new method for power estimation in nodes of multi-level combinational circuits and describe its application to the extraction of common expressions for low power design. It is assumed that each node is implemented as a complex gate and the capacitance and the switching activity of the nodes are considered in the power estimation. Extracting common expressions which is accomplished mostly by the extraction of kernels, can be transformed to the problem of rectangle covering. We describe how the newly proposed estimation method can be applied to the rectangle covering problem and show the experimental results with comparisons to the results of SIS-1.2.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(1)
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• pp.413-416
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• 2001

In high frequency range, RF circuit design without considering shielding effect can cause several significant changes due to increase in parasitic capacitance and inductance between RF signal lines and shielding box. In this paper, bandpass filter has been made to measure the shielding effect and its s-parameter has been measured by Vector Network Analyzer (VNA). Equivalent circuit model including the shielding effect has been constructed with the lumped elements extracted from the 3D electromagnetic simulator, Maxwell SI. Then, the validity of the model is verified using microwave circuit simulator, ADS (Advanced Design System).

• 전자공학회논문지
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• 제53권11호
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• pp.25-31
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• 2016

FinFET의 기생 커패시턴스와 기생저항은 회로의 고주파 성능을 결정하는 매우 중요한 요소이다. 선행 연구에서 BSIM-CMG에 구현된 FinFET의 기생 커패시턴스와 저항 모델보다 더 정확한 압축 모델을 개발하였다. 모델의 정확도를 검증하고, FinFET으로 구현 가능한 RF 회로의 성능을 정확하게 예측하기 위해 $S_{21}$ 10dB 이상 중심 주파수 60GHz 이상을 갖는 Low Noise Amplifier (LNA) 에 설계하였다. 22 nm FinFET 소자의 압축모델에 기반한 HSPICE를 사용하여 예측한 회로 성능의 정확도를 검증하기 위해 3D TCAD simulator인 Sentaurus의 mixed-mode 기능을 사용하여 LNA를 시뮬레이션 하였다. TCAD 시뮬레이션 결과를 정확도 측정의 기준으로 삼아 10GHz~100GHz 대역에서 제안한 모델과 Sentaurus의 $S_{21}$을 비교한 결과 87.5%의 정확도를 달성하였다. 이는 기존의 BSIM-CMG의 기생성분으로 예측한 정확도가 56.5%도임에 비해 31% 향상된 정확도를 보여준다. 이를 통해 FinFET의 기생 성분 모델의 정확도를 RF 영역에서 확인하였고, 정확한 기생 저항과 커패시턴스 모델이 LNA 성능을 정확하게 예측하는데 중요한 것임을 확인하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 C
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• pp.1841-1843
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• 2001

Asymmetrical parallel coupled lines are used in a number of circuits such as multi-band coupler and combline type band pass filter. Although graphical results and formulas are available for the design of coupled lines, the design procedure is hard to use, because even- and odd- mode impedances are always expressed in terms of the physical geometry. In this paper, we introduce a method to find design parameter using finite element analysis. By employing the capacitance obtained by FE analysis, design parameters for each lines are extracted. To show the validity of extracted design parameter for asymmetrical parallel coupled line, we have designed and simulated a planar type combline band pass filter.

• 대한전기학회논문지
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• 제35권12호
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• pp.560-566
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• 1986

In the design of an RF discharge system, the electrical equivalence of the gas discharge must be known. With this knowledge, one can design a suitable matching network for a maximum power transfer from the RF generator into the discharge. For this purpose, an experiment has been conducted in which the electrical impedance (conductance and capacitance) was determined as a function of power. In parallel with this, a detailed theoretical analysis has been done and the results are in accord with those of our experiment. Design equations are also given for a simple matching network, and a design example is presented to demonstrate its application. During the actual operation of an RF discharge system, however, it has been often observed that the reflected power tends to vary in small values due to the changes in the impedance of the system. This problem can be relieved by adding an automatic impedance matching circuit to the system and this paper presents such an automatic impedance matching network.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권6호
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• pp.416-428
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• 1999

A user-interactive pixel design tool for high-quality TFT-LCDs is realized and used to explore the sensitivity of the various array and device parameters for optimizing pixel design. In this tool, the Thompson cable equation and gradual-channel approximation were used for the gate time delay and TFT current modeling respectively. With this tool, each capacitance element, and TFT and array dimensions can be optimized under given design specifications. The electrical characteristics such ascharging ratio, gate time delay, pixel voltage level-shift, and holding ratio can be analyzed. The sensitivity analysis of those design parameters were executed and presented.

• 전기전자학회논문지
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• 제13권2호
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• pp.194-199
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• 2009

본 논문에서는 부분방전 시스템 응용을 위한 특 고압 80 pF (17kV AC) 마이카 커패시터를 연구하였다. 그리고 커패시터를 설계하기 위한 프로그램이 직병렬 파라미터를 추출하도록 개발되었다. 마이카는 커패시터의 유전체로 사용되었다. 30mm$\times$35mm 크키의 50$\mu$m 두께 마이카 시트가 병렬 커패시터 요소를 형성하도록 연박과 사용되었다. 20개의 마이카 시트는 커패시터의 요구에 맞추어 병렬 커패시터 요소의 직렬 스택을 형성하도록 연박으로 분리되었다. 17kV AC에 대한 제작된 80pF 커패시터의 크기는 90mm$\times$90mm이다. 제작된 커패시터에 대한 커패시턴스(C)와 손실률(D)의 고주파수 특성은 커패시턴스 메타를 사용하여 측정되었다. 제작된 커패시터는 150kHz$\sim$50MHz 주파수 범위에서 79.5pF의 커패시턴스와 0.001%의 손실률을 갖고, 65MHz에서 자기공진주파수를 가진다.