• The Journal of the Acoustical Society of Korea
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• v.20 no.8
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• pp.19-23
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• 2001

DSP-based implementation is pervasive in wireless communication parts for systems and handsets according to developing high-speed and low-power programmable Digital Signal Processor (DSP). In this paper, we present a real-time implementation of multi-channel Adaptive Multi-rate (AMR) speech coder. The real-time implementation of an AMR algorithm is achieved using 32-bit fixed-point TMS320C6202 DSP chip that operates at 250 MHz. We performed cross compile, linear assembly optimization and TMS320C62xx assembly optimization for real-time implementation. Furthermore, speech data input/output function and communication function with external CPU is included in an AMR speech coder. The AMR Speech coder developed using DSP EVM board was evaluated in ETRI IMT-2000 Test-bed system.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.2
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• pp.435-442
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• 2018

This study implemented an FPGA-based system to extract PCB defect patterns. The FPGA-based system can perform pattern matching at high speed for vision automation. An image processing library that is used to extract defect patterns was also implemented in IPs to optimize the system. The IPs implemented are Camera Link IP, Histogram IP, VGA IP, Horizontal Projection IP and Vertical Projection IP. In terms of hardware, the FPGA chip from the Vertex-5 of Xilinx was used to receive and handle images that are sent from a digital camera. This system uses MicroBlaze CPU. The image results are sent to PC and displayed on a 7inch TFT-LCD and monitor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11A
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• pp.1117-1123
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• 2008

Applications for mobile multimedia are testing the performance limits of present day CPUs with variety. However, hardwired solutions are inflexible and expensive to develop. CPUs with flexibility have limitation of performance. So, the requirement for both ASIC-like performance and CPU-like flexibility has led to reconfigurable processor. Mobile systems require low power and high performance concurrently. In this paper, we propose reconfigurable processor for mobile multimedia with high energy efficiency. Reconfigurable processor with 121MOPS/mW is developed by 130nm CMOS technology. And the processor was simulated for energy efficiency with 539MOPS/mW by 90nm CMOS technology and effective use of instructions. And we tested its applications for multimedia field. We tested the case of inverse MDCT for MP3 and DF for MPEG4 and ME for H.264.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.3
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• pp.213-218
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• 2008

This paper describes hardware-based high speed multimedia data reassembly processor for remote multimedia Set-Top-Box(MSTB) of interactive satellite multimedia communication system. The conventional multimedia data reassembly scheme is based on software processing of MSTB. As increasing of transmission rate for multimedia data services, the CPU load of remote MSTB is increased and reassembly performance of MSTB is limited. To provide high speed multimedia data service to end user, we proposed hardware based high speed multimedia data reassembly processor. It is implemented by using an FPGA, a PCI interface chip, and RAMs. And it is integrated in MSTB and tested. It has been confirmed to meet required all functions and processing rate up to 116Mbps.

• The Journal of the Korea Contents Association
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• v.15 no.9
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• pp.21-28
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• 2015

In the semi-conductor process, a simulation process is performed to detect defects by analyzing the behavior of the impurity through the physical quantity calculation of the inner element. In order to perform the simulation, Finite-Difference Time-Domain(FDTD) algorithm is used. The improvement of semiconductor which is composed of nanoscale elements, the size of simulation is getting bigger. Problems that a processor such as CPU or GPU cannot perform the simulation due to the massive size of matrix or a computer consist of multiple processors cannot handle a massive FDTD may come up. For those problems, studies are performed with parallel/distributed computing. However, in the past, only single type of processor was used. In GPU's case, it performs fast, but at the same time, it has limited memory. On the other hand, in CPU, it performs slower than that of GPU. To solve the problem, we implemented a computing model that can handle any FDTD simulation regardless of size on the cluster which consist of heterogeneous processors. We tested the simulation on processors using MPI libraries which is based on 'point to point' communication and verified that it operates correctly regardless of the number of node and type. Also, we analyzed the performance by measuring the total execution time and specific time for the simulation on each test.

• Proceedings of the Korean Society of Computer Information Conference
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• 2013.01a
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• pp.205-206
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• 2013

본 논문에서는 스마트폰, 스마트 태블릿, 스마트 패드등과 로봇 구동장치를 결합하여 스마트 로봇 시스템을 효율적으로 개발하는 방법을 소개 한다. 스마트 디바이스 보급은 가속화 되어 많은 분야에 스마트 디바이스를 사용하고 있다. 스마트 디바이스의 CPU의 성능 효율이 좋아 멀티미디어와 인식이 가능하며, 내장된 GPS 칩과 자이로 센서 및 네트워크등 다양한 디바이스를 연결하게 되면 효율적인 정보를 얻어 낼 수 있다. 스마트 디바이스의 판단 처리 및 멀티미디어 출력 기능에 로봇의 구동 장치를 결합하여 스마트 로봇을 만들어 내면 다양한 분야에 효율적으로 사용이 가능하다. 본 논문은 스마트 디바이스에서 인식되는 다양한 패턴과 로봇 구동장치의 효율적인 결합 방법을 설명한다.

• Electronics and Telecommunications Trends
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• v.25 no.5
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• pp.33-46
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• 2010

인쇄전자회로 기술은 인쇄(graphic art printing) 공정을 활용한 다양한 광/전자 기기 개발을 위한 핵심요소 기술이다. 기능성 전자 잉크 소재와 초저가격의 프린팅 공정을 통해서 유비쿼터스 시대의 차세대 모바일 IT 기기의 생명력을 불어넣게 된다. 현재 기술 수준이 일부 요소 부품들을 제작하고 기본 단위의 정보처리를 가능케 하는 수준에 머무르고 있으나, 여러 가지 잉크 소재 및 다양한 초미세 인쇄 공정 기술의 개발이 진행됨에 따라 향후 폭넓은 분양에 적용될 것으로 기대된다. 궁극적으로 인쇄전자회로의 성능이 향상되고 고집적화 됨으로써 기존의 Si 기반 CPU나 IC 칩을 대체하는 공정으로 자리매김을 할 것으로 예상된다. 본 기고문에서는 이러한 인쇄전자회로 기술 및 동향에 대해 기술하였다. 특히, 현재 폭넓게 연구가 진행중인 차세대 디스플레이 백플레인이나 개별물품단위 트래킹을 위한 플라스틱 RFID 태그 적용을 위해 필요한 요건들을 인쇄전자회로 기술관점에서 조망하였다.

• Proceedings of the KSME Conference
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• 2000.04b
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• pp.353-358
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• 2000

This paper presents the experimental investigation about miniature heat pipe for notebook PC. The focus of analysis is the operating temperature not to exceed $65^{\circ}C$ maximum allowable CPU surface temperature. Copper is used to heat pipe material and brass is wick material, and working fluid is selected to water. This cooling system is heat spreader method using a aluminum plate, since this method is most commonly used. According to the present study, heat for 3mm heat pipe, 8W, and for 4mm heat pipe, 10W, is found to power dissipation limit respectively, Soon after this investigation, sufficient long term life test should be followed.

• Proceedings of the Korean Information Science Society Conference
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• 2006.06a
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• pp.355-357
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• 2006

반도체 공정의 발달로 인해 하나의 칩에 많은 양의 소자를 넣는 것이 가능해지면서 상대적으로 넓어진 공간에서 캐시 메모리가 차지하는 공간의 비중이 증가하고 있다. 상대적으로 비중이 커진 캐시 메모리는 CPU가 소모하는 전력의 50%에 상당하는 전력을 소모하는 등 시스템의 성능뿐만 아니라 전력 소모에도 큰 영향을 주고 있다. 현재 시스템 성능 향상과 전력 소모 절감을 위하여 캐시 메모리의 논리적 구조를 개선하기 위한 많은 연구가 진행 중이다. 본 논문에서는 다양한 용도로 사용되는 범용 시스템이 아닌 특정 응용분야에 최적화되어 사용되는 소규모 임베디드 시스템에 적합한 직접사상캐시를 위한 재구성 가능한 백업캐시를 제안하려고 한다. 제안하는 백업 캐시는 특정 레지스터 값을 이용해서 백업캐시를 재구성 가능하게 하여 응용분야에 따라 직접사상캐시의 성능 향상과 전력소모를 절감하도록 하여 시스템의 성능향상과 전력소모를 절감시키는 역할을 할 것이다.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.671-672
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• 2006

Recently Communication with using IrDA is bing used in various fields. In this paper I designed a receiver by fabricating hardware that used to be fabricated through software, so anyone who don't have knowledge on IrDA can receive Ir Signal easily. This receiver can communicate with CPU through 8 bit data and 3 bit address. Also this receiver can use user-needed CLK because this receiver embodied 16 bit CLK Prescaler.