• The Journal of the Korea Contents Association
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• v.9 no.2
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• pp.76-87
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• 2009

The growth of CPU and communication technologies have made an important contribution to the development of the network-based intelligent service robots. Robot software must guarantee the correct execution and safety of the user. To achieve this, it is highly required to research how to guarantee the QoS of the components which organize a robot software. The QoS of robot components aims to execute the component stably by processing the data stream in a correct way. By guaranteeing QoS, we can achieve the intelligence and stability of robots. In this paper, we design and implement the QoS framework to guarantee the QoS of robot components on robot platforms with limited resources. We also measure the response times of QoS requests and present the performance analysis results about it.

• KIISE Transactions on Computing Practices
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• v.21 no.1
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• pp.29-39
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• 2015

When new inertial navigation systems for an unmanned aerial vehicles are being developed and tested, construction of a fault-tolerant system is required because of various types of hazards caused by S/W and H/W faults. In this paper, a new fault-tolerant flight system that can be deployed into one or more FCCs (Flight Control Computers) is introduced, based on a partition scheme wherein each OFP (Operational Flight Program) partition uses an independent CPU and memory slot. The new fault-tolerant navigation system utilizes one or two FCCs, and executes a primary navigation OFP under development and a stable shadow OFP partition on each node. The fault-tolerant navigation system based on a single FCC can be used for UAVs with small payloads. For larger UAVs, an additional FCC with two OFP partitions can be used to provide both H/W and S/W fault-tolerance. The developed fault-tolerant navigation system significantly removes various hazards in testing new navigation S/Ws for UAVs.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.4
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• pp.507-511
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• 2010

In this paper, we propose to enhance the performance of software transcoder by using GPGPU for scaling filters. Video transcoding is a technique that translates a video file to another video file that has a different coding algorithm and/or a different frame size. Its demand increases as more multimedia devices with different specification coexist in our daily life. Since transcoding is computationally intensive, a software transcoder that runs on a CPU takes long processing time. In this paper, we achieve significant speed-up by parallelizing the scaling filter using a GPGPU that can provide significantly large computation power. Through extensive experiments with various video scripts of different size and with various scaling filter options, it is verified that the enhanced transcoder could achieve 36% performance improvement in the default option, and up to 101% in a certain option.

• Journal of the Korea Society of Computer and Information
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• v.19 no.4
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• pp.9-16
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• 2014

This paper proposes a linear scratch detection and restoration algorithm using pixel data comparison in a single frame or consecutive frames. There exists a high parallelism in that a scratch detection and restoration algorithm needs a large amount of comparison operations. The proposed scratch detection and restoration algorithm is designed with a GPU for fast computation. We test the proposed algorithm in sequential and parallel processing with the set of digital videos in National Archive of Korea. In the experiments, the scratch detection rate of consecutive frames is as fast as about 20% for that of a single frame. The detection and restoration rates of a GPU-based algorithm are similar to those of a CPU-based algorithm, but the parallel implementation speeds up to about 50 times.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.308-311
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• 2015

Because worldwide interest in the health is increased, the real-time health monitoring system has been demanded to be more convenient non-contact and precise medical devices than conventional. Therefore we developed the blood pressure monitoring system using UWB(Ultra Wide Band) radio wave which contact to the human body through the radar and continuously collect a movement signal of the blood vessel. Then the collected data including pulse rate, systolic blood pressure, diastolic blood pressure is processed in real time. The system monitors and controls through a program-based embedded LCD(Liquid Crystal Display) using Qt GUI(Graphic User Interface) to be displayed in real time. We implement the system as a embedded system because of reducing the size of the limited resources. Existing PC GUI design mode is used relatively large memory, therefore it requires more CPU(Central Processing Unit) capacity and processing time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.16-25
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• 2002

This paper presents a methodology and application for extracting parasitic inductances in a multi-level interconnect semiconductor structure by a numerical technique. In order to calculate the parasitic inductances, the distrubution of electric potential and current density in the metal lines are calculated by finite element method (FEM). Thereafter, the magneto-static energy caused by the current density in metal lines was calculated. The result of simulation is compared with the result of Grover equation about analytic simple structures, and 4 bit ROM array with a dimension of $13{\times}10.25{\times}8.25{\mu}m^3$ was simulated to extract the parasitic inductnaces. In this calculation, 6,358 nodes with 31,941 tetrahedra were used in ULTRA 10 workstation. The total CPU time for the simulation was about 150 seconds, while the memory size of 20 MB was required.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.44-53
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• 1999

This paper are reported a methodology and application for extracting parasitic capacitances in a multi-level interconnect semiconductor structure by a numerical technique. To calculate the parasitic capacitances between the interconnect lines, we employed finite element method (FEM) and calculated the distrubution of electric potential in the inter-metal layer dielecric(ILD) by solving the Laplace equation. The three-dimensional multi-level interconnect structure is generated directly from two-dimensional mask layout data by specifying process sequences and dimension. An exemplary structure comprising two metal lines with a dimension of 8.0$\times$8.0$\times$5.0$\mu\textrm{m}^3/TEX>, which is embedded in three dielectric layer, was simulated to extract the parasitic capacitances. In this calculation, 1960 nodes with 8892 tetrahedra were used in ULTRA SPARC 1 workstation. The total CPU time for the simulation was 28 seconds, while the memory size of 4.4MB was required.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.7
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• pp.7-16
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• 2000

This paper reports a methodology and its application for extracting cell capacitances and parasitic capacitances in a stacked DRAM cell structure by a numerical technique. To calculate the cell and parasitic capacitances, we employed finite element method (FEM), The three-dimensional DRAM cell structure is generated by solid modeling based on two-dimensional mask layout and transfer data. To obtain transfer data for generating three-dimensional simulation structure, topography simulation is performed. In this calculation, an exemplary structure comprising 4 cell capacitors with a dimension of $2.25{\times}1.75{\times}3.45{\mu}m^3$, 70,078 nodes with 395,064 tetrahedra were used in ULTRA SPARC 10 workstation. The total CPU time for the simulation was about 25 minutes, while the memory size of 201MB was required. The calculated cell capacitance is 24.34fF per cell, and the influential parasitic capacitances in a stacked DRAM cell are investigated.

• Journal of Navigation and Port Research
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• v.32 no.3
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• pp.223-228
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• 2008

As most of small fishing boats made of FRP have been constructed by experience in Korea, some structural safety problems have been occurred occasionally. To improve the structural strength and reduce the costs for construction and operation, optimum design for small fishing boat was carried out in this study. The weight of fishing boat and the main dimensions of structural members are chosen as objective function and design variables, respectively. By the combination of global and local search methods, a hybrid optimization algorithm was developed to escape the local minima and reduce CPU time in analysis procedure, and finite element analysis was performed to determine the constraint parameters at each iteration step in optimization loop. Optimization results were compared with the real existing fishing boat, and the effects of optimum design were examined from points of view; structural strength, material cost, etc.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.6
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• pp.445-449
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• 2009

In this paper, we propose a computationally efficient multi GPU accelerated image registration technique to correct the motion difference between the pre-contrast CT image and post-contrast CTA image. Our method consists of two steps: multi GPU based image registration and a cerebrovascular visualization. At first, it computes a similarity measure considering the parallelism between both GPUs as well as the parallelism inside GPU for performing the voxel-based registration. Then, it subtracts a CT image transformed by optimal transformation matrix from CTA image, and visualizes the subtracted volume using GPU based volume rendering technique. In this paper, we compare our proposed method with existing methods using 5 pairs of pre-contrast brain CT image and post-contrast brain CTA image in order to prove the superiority of our method in regard to visual quality and computational time. Experimental results show that our method well visualizes a brain vessel, so it well diagnose a vessel disease. Our multi GPU based approach is 11.6 times faster than CPU based approach and 1.4 times faster than single GPU based approach for total processing.