• Nuclear Engineering and Technology
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• v.53 no.8
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• pp.2445-2453
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• 2021

Since the nuclear data forms a vital component in reactor physics computations, the nuclear community needs processing codes as tools for translating the Evaluated Nuclear Data Files (ENDF) to simulate nuclear-related problems such as an ACE format that is used for MCNP. Errors, inaccuracies or discrepancies in library processing may lead to a calculation that disagrees with the experimentally measured benchmark. This paper provides an overview of the processing and preparation of ENDF/B-VIII.0 incident neutron data with NECP-Atlas and NJOY codes for implementation in the MCNP code. The resulting libraries are statistically inter-compared and tested by conducting benchmark calculations, as the mutualcomparison is a source of strong feedback for further improvements in processing procedures. The database of the benchmark experiments is based on a selection taken from the International Handbook of Evaluated Criticality Safety Benchmark Experiments (ICSBEP handbook) and those proposed by Russell D. Mosteller. In general, there is quite good agreement between the NECP-Atlas1.2 and NJOY21^(1.0.0.json) results with no substantial differences, if the correct input parameters are used.

• Nuclear Engineering and Technology
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• v.53 no.1
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• pp.337-343
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• 2021

In this work, self-absorption correction factor related to the variation of the composition and the density of soil samples were evaluated using the p-type HPGe detector. The validated MCNP5 simulation model of this detector was used to evaluate its Full Energy Peak Efficiency (FEPE) under the variation of the composition and the density of the analysed samples. The results indicates that FEPE calculation of low gamma ray is affected by the composition and the density of soil samples. The self-absorption correction factors for different gamma-ray energies which was fitted as a function of FEPEs via density and energy and fitting parameters as polynomial function for the logarithm neper of gamma ray energy help to calculate quickly the detection efficiency of detector. Factor Analysis for the influence of the element composition in analysed samples on the FEPE indicates the FEPE distribution changes from non-metal to metal groups when the gamma ray energy increases from 92 keV to 238 keV. At energies above 238 keV, the FEPE primarily depends only on the metal elements and is significantly affected by aluminium and silicon composition in soil samples.

• Nuclear Engineering and Technology
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• v.55 no.8
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• pp.3102-3113
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• 2023

Following the Fukushima nuclear disaster, the simulation of accidents in the spent fuel pool has become more noticeable. Despite the low amount of decay heat power, the consequences of the accidents in a spent fuel pool (SFP) can be severe due to the high content of long-lived radionuclides and lack of protection by the pressure vessel. In this study, the loss-of-cooling accident (LOFA) for the VVER-1000/V446 spent fuel pool is simulated by employing RELAP5 and MELCOR 1.8.6 as the best estimate and severe accident analysis codes, respectively. For two cases with different total power levels, decay heat of spent fuels is calculated by ORIGEN-II code. For modeling SFP of a VVER-1000, a qualified nodalizations are considered in both codes. During LOFA in SFP, the key sequences such as heating up of the pool water, boiling and reducing the water level, uncovering the spent fuels, increasing the temperature of the spent fuels, starting oxidation process (generating Hydrogen and extra power), the onset of fuel melting, and finally releasing radionuclides are studied for both cases. The obtained results show a reasonable consistency between the RELAP5 and MELCOR codes, especially before starting the oxidation process.

• Nuclear Engineering and Technology
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• v.55 no.5
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• pp.1885-1891
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• 2023

The present work aims to fabricate Na_1+xZr₂Si_xP_3-xO₁₂ compound at various calcination temperatures based on the zircon mineral. The fabricated compound was calcinated at 250, 500, and 1000℃. The effect of calcination temperature on the structure, crystal phase, and radiation shielding properties was studied for the fabricated compound. The X-ray diffraction diffractometer demonstrates that, the monoclinic crystal phase appeared at a calcination temperature of 250℃ and 500℃ is totally transformed to a high-symmetry hexagonal crystal phase under a calcination temperature of 1000℃. The radiation shielding capacity was also qualified for the fabricated compounds using the Monte Carlo N-Particle transport code in the g-photons energy interval between 15keV and 122keV. The impacts of calcination temperature on the g-ray shielding behavior were clarified in the present study, where the linear attenuation coefficient was enhanced by 218% at energy of 122keV, when the calcination temperature increased from 250 to 1000℃, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.121-124
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• 2008

In this paper, we will design a 800MHz broadband antenna after a problem of the narrow bandwidth is improved. This multiple band antenna unifies the CDMA(Code Division Multiple Access), GSM(Global System for Mobile telecommunication) and TRS(Trunked Radio System) band in the UHF bandwidth, and then it is possible at the shore base station or repeater as the commercial use. It used the duplex resonance effect It had the L-shaped feeding structure which adds the V-slot. And it improved profit using stack structure. It was measured that the frequency bandwidth of the designed antenna which is planed $792{\sim}1040MHz$ with 248MHz(33%). And the antenna gain is 9.4dBi, 3dB beam width $60^{\circ}$ in radiation pattern.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.715-722
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• 2010

This paper describes a hardware design of hash function processor which implements Korean Hash Algorithm Standard HAS-160. The HAS-160 processor compresses a message with arbitrary lengths into a hash code with a fixed length of 160-bit. To achieve high-speed operation with small-area, arithmetic operation for step-operation is implemented by using a hybrid structure of 5:3 and 3:2 carry-save adders and carry-select adder. It computes a 160-bit hash code from a message block of 512 bits in 82 clock cycles, and has 312 Mbps throughput at 50 MHz@3.3-V clock frequency. The designed HAS-160 processor is verified by FPGA implementation, and it has 17,600 gates on a layout area of about $1\;mm^2$ using a 0.35-${\mu}m$ CMOS cell library.

• Journal of the Earthquake Engineering Society of Korea
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• v.20 no.4
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• pp.257-268
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• 2016

In the companion papers (I, II), site-specific response analyses were performed at more than 300 domestic sites and a new site classification system and design response spectra (DRS) were proposed using the results of the site-specific response analyses. In this paper, the proposed site classification system and the design response spectra are compared with those in other seismic codes and verified by different methods. Firstly, the design response spectra are compared with the design response spectra in Eurocode 8, KBC 2016 and MOCT 1997 to estimate quantitative differences and general trends. Secondly, site-specific response analyses are carried out using $V_S$-profiles obtained using field seismic tests and the results are compared with the proposed DRS in order to reduce the uncertainty in using the SPT-N value in site-specific response analyses in the companion paper (I). In addition, site coefficients from real earthquake records measured in Korean peninsula are used to compare with the proposed site coefficients. Finally, dynamic centrifuge tests are also performed to simulate the representative Korean site conditions, such as shallow depth to bedrock and short-period amplification characteristics. The overall results showed that the proposed site classification system and design response spectra reasonably represented the site amplification characteristic of shallow bedrock condition in Korea.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.2
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• pp.111-116
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• 2003

In this paper, a CMOS baseband analog receiver for wireless home network is discussed. It is composed of a Gilbert type mixer, an Elliptic 6th order 1ow pass filter, and a 6-bit A/D converter. The main role of the mixer is generating a mixed analog signal between the 200MHz output signal of CMOS RF stage and the 199MHz local oscillator. After the undesired high frequency component of the mixed signal comes out. Finally, the analog signal is converted into digital code at the 6-bit A/D converter, The proposed receiver is fabricated with 0.25${\mu}{\textrm}{m}$ 1-poly 5-metal CMOS technology, and the chip area is 200${\mu}{\textrm}{m}$ X1400${\mu}{\textrm}{m}$. the receiver consumes 130㎽ at 2.5V power supply.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.777-780
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• 2005

모바일 오디오 적용을 위한 저전력 ${\Sigma}{\Delta}$ Modulator 에 대한 설계와 layout 을 보였다. 전체 구조는 3 차 단일 피드백 루프이며, 해상도는 16bit 을 갖는다. 샘플링 주파수에 따른 Over-sampling Ratio 는 128(46kHz) 또는 64(96kHz) 가 되도록 하였다. 차동 구조를 사용한 3 차 ${\Sigma}{\Delta}$ modulator 내의 적분기에 사용된 Op-Amp 는 DC-Gain 을 높이기 위해서 Gain-boosting 기법이 적용되었다. ${\Sigma}{\Delta}$ modulator 의 기준 전압은 전류 모드 Band-Gap Reference 회로에서 공급이 되며, PVT(Process, Voltage, Temperature) 변화에 따른 기준 전압의 편차를 보정하기 위하여, binary 3bit 으로 선택하도록 하였다. DAC 에서 사용되는 단위 커패시터의 mismatch 에 의한 성능 감소를 막기 위해, DAC 신호의 경로를 임의적으로 바꿔주는 scrambler 회로를 이용하였다. 4bit Quantizer 내부의 비교기 회로는 고해상도를 갖도록 설계하였고, 16bit thermometer code 에서 4bit binary code 변환시 발생하는 에러를 줄이기 위해 thermometer-to-gray, gray-to-binary 인코딩 방법을 적용하였다. 0.18um CMOS standard logic 공정 내 thick oxide transistor(3.3V supply) 공정을 이용하였다. 입력 전압 범위는 2.2Vp-p,diff. 이며, Typical process, 3.3V supply, 50' C 시뮬레이션 조건에서 2Vpp,diff. 20kHz sine wave 를 입력으로 할 때 SNR 110dB, THD 는 -95dB 이상의 성능을 보였고, 전류 소모는 6.67mA 이다. 또한 전체 layout 크기는 가로 1100um, 세로 840um 이다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.18-26
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n wireless LAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. From fixed-point modeling and Matlab simulations for various bit-widths, decoding performance and optimal hardware parameters such as fixed-point bit-width are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.18-${\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.