• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.37-41
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• 2012

The wafer level stacking with Cu-to-Cu bonding becomes an important technology for high density DRAM stacking, high performance logic stacking, or heterogeneous chip stacking. Cu CMP becomes one of key processes to be developed for optimized Cu bonding process. For the ultra low-k dielectrics used in the advanced logic applications, Ti barrier has been preferred due to its good compatibility with porous ultra low-K dielectrics. But since Ti is electrochemically reactive to Cu CMP slurries, it leads to a new challenge to Cu CMP. In this study Ti barrier/Cu interconnection structure has been investigated for the wafer level 3D integration. Cu CMP wafers have been fabricated by a damascene process and two types of slurry were compared. The slurry selectivity to $SiO_2$ and Ti and removal rate were measured. The effect of metal line width and metal density were evaluated.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.46-49
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• 2003

Chemical mechanical polishing (CMP) is an essential dielectric planarization in multilayer microelectronic device fabrication. In the CMP process it is necessary to minimize the extent of surface defect formation while maintaining good planarity and optimal material removal rates. The polishing mechanism of W-CMP process has been reported as the repeated process of passive layer formation by oxidizer and abrasion action by slurry abrasives. Thus, it is important to understand the effect of oxidizer on W passivation layer, in order to obtain higher removal rate (RR) and very low non-uniformity (NU%) during W-CMP process. In this paper, we compared the effects of oxidizer or W-CMP process with three different kind of oxidizers with 5% hydrogen peroxide such as $Fe(NO_3)_3$, $H_2O_2$, and $KIO_3$. The difference in removal rate and roughness of W in stable and unstable slurries are believed to caused by modification in the mechanical behavior of $Al_3O_3$ particles in presence of surfactant stabilizing the slurry.

• Korean Journal of Materials Research
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• v.16 no.12
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• pp.731-738
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• 2006

It is seriously considered using Al CMP (chemical mechanical planarization) process for the next generation 45 nm Al wiring process. Al CMP is known that it has a possibility of reducing process time and steps comparing with conventional RIE (reactive ion etching) method. Also, it is more cost effective than Cu CMP and better electrical conductivity than W via process. In this study, we investigated 4 different kinds of slurries based on abrasives for reducing scratches which contributed to make defects in Al CMP. The abrasives used in this experiment were alumina, fumed silica, alkaline colloidal silica, and acidic colloidal silica. Al CMP process was conducted as functions of abrasive contents, $H_3PO_4$ contents and pressures to find out the optimized parameters and conditions. Al removal rates were slowed over 2 wt% of slurry contents in all types of slurries. The removal rates of alumina and fumed silica slurries were increased by phosphoric acid but acidic colloidal slurry was slightly increased at 2 vol% and soon decreased. The excessive addition of phosphoric acid affected the particle size distributions and increased scratches. Polishing pressure increased not only the removal rate but also the surface scratches. Acidic colloidal silica slurry showed the highest removal rate and the lowest roughness values among the 4 different slurry types.

• Journal of the Semiconductor & Display Technology
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• v.10 no.4
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• pp.139-144
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• 2011

CMP process is an essential element in the semiconductor product processes in Chemical Mechanical Polishing. Taken as a whole, CMP is one process, but concretely, it is a detail process which consists of polishing, cleaning, and so on. Especially, the polishing and cleaning are key points in the whole process. Polishing rate is the most important factor and is related with deposition of slurry in the polishing process. Each outlet velocities is the most important factors in cleaning process. And when the velocities are more uniform, the cleaning becomes more effective. In this research, based on these factors, we performed a numerical analysis for effective polishing and cleaning which can be applied to industrial field. Consequently, we figured out that more than one opened nozzle is more effective than one opened nozzle at the polishing pad in case of this research. And we confirmed that the revised models have the uniform velocity distribution more than the previous model of the cleaning nozzle.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.707-710
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• 2004

Chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of in the defect-free inter-level dielectrics (ILD). In this paper, we have investigated slurry properties and CMP performance of silicon dioxide (oxide) as a function of different temperature of slurry. Thermal effects on the silica slurry properties such as pH, particle size, conductivity and zeta potential were studied. Moreover, the relationship between the removal rate (RR) with WIWNU and slurry properties caused by changes of temperature were investigated. Therefore, the understanding of these temperature effects provides a foundation to optimize an oxide CMP Process for ULSI multi-level interconnection technology.

• Transactions of Materials Processing
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• v.13 no.3
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• pp.225-229
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• 2004

Chemical Mechanical Polishing(CMP) process becomes one of the most important semiconductor processes. But the basic mechanism of CMP still does not established. Slurry fluid dynamics that there is a slurry film between a wafer and a pad and contact mechanics that a wafer and a pad contact directly are the two main studies for CMP. This paper based on the latter one, especially on the abrasion wear model. Material Removal Rate(MRR) is calculated using the trajectory length of every point on a wafer during the process time. Both the rotational velocity of a wafer and a pad and the wafer oscillation velocity which has omitted in other studies are considered. For the purpose of the verification of our simulation, we used the experimental results of S.H.Li et al. The simulation results show that the tendency of the calculated MRR using the relative velocity is very similar to the experimental results and that the oscillation effect on MRR at a real CMP condition is lower than 1.5%, which is higher than the relative velocity effect of wafer, and that the velocity factor. not the velocity itself, should be taken into consideration in the CMP wear model.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.39-42
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• 2002

Recently, CMP (chemical mechanical polishing) technology has been widely used for global planarization of multi-level interconnection for ULSI applications. However, COO (cost of ownership) and COC (cost of consumables) were relatively increased because of expensive slurry. In this paper, we have studied the possibility of recycle of reused silica slurry in order to reduce the costs of CMP slurry. The post-CMP thickness and within-wafer non-uniformity(WIWNU) were measured as a function of different slurry composition. As a experimental result, the performance of reused slurry with annealed silica abrasive of 2 wt% contents was showed high removal rate and low non-uniformity. Therefore, we propose two-step CMP process as follows In the first-step CMP, we can polish the thick and rough film surface using remaked slurry, and then, in the second-step CMP, we can polish the thin film and fine pattern using original slurry. In summary, we can expect the saving of high costs of slurry.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.9
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• pp.759-764
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• 2003

Recently, CMP (chemical mechanical polishing) technology has been widely used for global planarization of multi-level interconnection for ULSI applications. However, COO (cost of ownership) and COC (cost of consumables) were relatively increased because of expensive slurry. In this paper, we have studied the possibility of recycle of roused silica slurry in order to reduce the costs of CMP slurry. The post-CMP thickness and within-wafer non-uniformity (WIWNU) wore measured as a function of different slurry composition. As an experimental result, the performance of reused slurry with annealed silica abrasive of 2 wt％ contents was showed high removal rate and low non-uniformity. Therefore, we propose two-step CMP process as follows , In tile first-step CMP, we can polish the thick and rough film surface using remaked slurry, and then, in the second-step CMP, we can polish the thin film and fine pattern using original slurry. In summary, we can expect the saying of high costs of slurry.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2002.05a
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• pp.272-278
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• 2002

Recently, STI(Shallow Trench Isolation) process has attracted attention for high density of semiconductor device as a essential isolation technology. In this paper, the effect of pattern density, trench width and selectivity of slurry on dishing in STI CMP process was investigated by using specially designed isolation pattern. As trench width increased, the dishing tends to increase. At $20{\mu}m$ pattern size, the dishing was decreased with increasing pattern density Low selectivity slurry shows less dishing at over $160{\mu}m$ trench width, whereas high selectivity slurry shows less dishing at below $160{\mu}m$ trench width.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.35-38
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• 2000

In this study, the rise throughput and the stability in fabrication of device can be obtained by applying of CMP process to STI structure in 0.l8um semiconductor device. Through reverse moat pattern process, reduced moat density at high moat density, STI CMP process with low selectivity could be to fit polish uniformity between low moat density and high moat density. Because this reason, in-situ motor current end point detection method is not fit to the current EPD technology with the reverse moat pattern. But we use HSS without reverse moat pattern on STI CMP and take end point current sensing signal.[1] To analyze sensing signal and test extracted signal, we can to adjust wafer difference within $110{\AA}$.