• 한국전기전자재료학회논문지
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• 제15권10호
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• pp.838-843
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• 2002

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The reverse moat etch process has been used for the shallow trench isolation(STI)-chemical mechanical polishing(CMP) process with conventional low selectivity slurries. Thus, the process became more complex, and the defects were seriously increased. In this paper, we studied the direct STI-CMP process without reverse moat etch step using high selectivity slurry(HSS). As our experimental results show, it was possible to achieve a global planarization without the complicated reverse moat process, the STI-CMP process could be dramatically simplified, and the defect level was reduced. Therefore the throughput, yield, and stability in the ULSI semiconductor device fabrication could be greatly improved.

• Tribology and Lubricants
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• 제30권3호
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• pp.139-145
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• 2014

Nowadays, most micro-patterns are manufactured during flow line production. However, a conventional rotary chemical mechanical polishing (CMP) system has a limited throughput for the fabrication of large and flexible electronics. To overcome this problem, we propose a novel linear roll-CMP system for the planarization of large-area electronics. In this paper, we present a statistical analysis on the linear roll-CMP process of copper-clad laminate (CCL) to determine the impacts of process parameters on the material removal rate (MRR) and its non-uniformity (NU). In the linear roll-CMP process, process parameters such as the slurry flow rate, roll speed, table feed rate, and down force affect the MRR and NU. To determine the polishing characteristics of roll-CMP, we use Taguchi's orthogonal array L16 (44) for the experimental design and F-values obtained by the analysis of variance (ANOVA). We investigate the signal-to-noise (S/N) ratio to identify the prominent control parameters. The "higher is better" for the MRR and "lower is better" for the NU were selected for obtaining optimum CMP performance characteristics. The experimental and statistical results indicate that the down force and roll speed mainly affect the MRR and the down force and table feed rate determine the NU in the linear roll-CMP process. However, over 186.3 N of down force deteriorates the NU because of the bending of substrate. Roll speed has little relationship to the NU and the table feed rate does not impact on the MRR. This study provides information on the design parameter of roll-CMP machine and process optimization.

• 한국전기전자재료학회논문지
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• 제14권7호
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• pp.557-561
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• 2001

Chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layers, which can be applied to the integraded circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of in the defect-free inter-level dielectrics (ILD). Especially, defects such as micro-scratch lead to severe circuit failure which affect yield. CMP slurries can contain particles exceeding 1㎛ in size, which could cause micro-scratch on the wafer surface. The large particles in these slurries may be caused by particles agglomeration in slurry supply line. To reduce these defects, slurry filtration method has been recommended in oxide CMP. In this work, we have studied the effects of filtration and the defect trend as a function of polished wafer count using various filters in inter-metal dielectrics(IMD)-CMP process. The filter installation in CMP polisher could reduce defects after IMD-CMP process. As a result of micro-scratch formation, it is shown that slurry filter plays an important role in determining consumable pad lifetime. The filter lifetime is dominated by the defects. We have concluded that slurry filter lifetime is fixed by the degree of generating defects.

• 한국기계가공학회지
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• 제18권8호
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• pp.44-50
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• 2019

CMP is the most critical process in the manufacture of silicon wafers, and the use of retaining rings, which are consumable parts used in CMP equipment, is increasingly important. Since the retaining ring is made of plastic, it is not only weak in strength but also has the problem of taking a long time for the flattening operation of the ring itself performed before the CMP process, and of the imbalance of force due to bolt tightening causing uneven wear. In order to solve this problem, the retaining ring and the insert ring are integrally used, and the flatness of the retaining ring may be affected depending on the material of the insert ring. Also, the residual stress generated in the manufacturing process of the insert ring may cause distortion of the ring, which may adversely affect the precision polishing. In this study, when the insert ring is made of Zn or STS304, the thickness variation and the flatness of the retaining ring are compared and, finally, the material removal rate is analyzed by polishing the wafer by the oxide CMP process. Through these experiments, the effects of the insert ring material on the polishing accuracy of the wafers were investigated.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.236-236
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• 2008

(Bi,La)$Ti_3O_{12}$(BLT) thin film is one of the most attractive materials for ferroelectric random access memory (FRAM) applications due to its some excellent properties such as high fatigue endurance, low processing temperature, and large remanent polarization [1-2]. The authors firstly investigated and reported the damascene process of chemical mechanical polishing (CMP) for BLT thin film capacitor on behalf of plasma etching process for fabrication of FRAM [3]. CMP process could prepare the BLT capacitors with the superior process efficiency to the plasma etching process without the well-known problems such as plasma damages and sloped sidewall, which was enough to apply to the fabrication of FRAM [2]. BLT-CMP characteristics showed the typical oxide-CMP characteristics which were related in both pressure and velocity according to Preston's equation and Hernandez's power law [2-4]. Good surface roughness was also obtained for the densification of multilevel memory structure by CMP process [3]. The well prepared BLT capacitors fabricated by CMP process should have the sufficient ferroelectric properties for FRAM; therefore, in this study the electrical properties of the BLT capacitor fabricated by CMP process were analyzed with the process parameters. Especially, the effects of CMP pressure, which had mainly affected the removal rate of BLT thin films [2], on the electrical properties were investigated. In order to check the influences of the pressure in eMP process on the ferroelectric properties of BLT thin films, the electrical test of the BLT capacitors was performed. The polarization-voltage (P-V) characteristics show a decreased the remanent polarization (Pr) value when CMP process was performed with the high pressure. The shape of the hysteresis loop is close to typical loop of BLT thin films in case of the specimen after CMP process with the pressures of 4.9 kPa; however, the shape of the hysteresis loop is not saturated due to high leakage current caused by structural and/or chemical damages in case of the specimen after CMP process with the pressures of 29.4 kPa. The leakage current density obtained with positive bias is one order lower than that with negative bias in case of 29.4 kPa, which was one or two order higher than in case of 4.9 kPa. The high pressure condition was not suitable for the damascene process of BLT thin films due to the defects in electrical properties although the better efficiency of process. by higher removal rate of BLT thin films was obtained with the high pressure of 29.4 kPa in the previous study [2].

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
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• pp.176-180
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• 2001

There are several factors causing re-work in CMP process such as improper polish time calculation by operator. removal rate decline of the polisher, unstable in-suit pad conditioning, slurry supply module problem and wafer carrier rotation inconsistancy. And conclusively those fundimental reason for the re-work rate increasement is mainly from the cycle time delay between wafer polish and post measurement. Therefore, Wafer thickness measurement in wet condition could be able to remove those improper process conditions which may happen during the process in comparison with the conventional dried wafer measurement system and it can be able to reduce the CMP process cycle time. CMP scrap reduction by overpolish, re-work rate reduction, thickness control efficiency also can be easily achieved. CMP Equipment manufacturer also trying to develop integrated system which has multi-head & platen, cleaner, pre & post thickness measure and even control the polish time from the calculated removal rate of each polishing head by software. CMP re-work problem such as over & under polish by target thickness may result in the cycle time delay. By reducing those inefficient factors during the process and establish of the automatic process control, CLC system need to be adopted to maximize the process performance. Wafer to Wafer Polish Time Feed Back Control by measuring the wafer right after the polish shorten the polish time calculation for the next wafer and it lead to the perfact Post CMP target thickness control capability. By Monitoring all of the processed the wafer, CMP process will also be stabilize itself.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집
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• pp.176-180
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• 2001

There are several factors causing re-work in CMP process such as improper polish time calculation by operator, removal rate decline of the polisher, unstable in-suit pad conditioning, slurry supply module problem and wafer carrier rotation inconsistency. And conclusively those fundimental reason for the re-work rate increasement is mainly from the cycle time delay between wafer polish and post measurement. Therefore, Wafer thickness measurement in wet condition could be able to remove those improper process conditions which may happen during the process in comparison with the conventional dried wafer measurement system and it can be able to reduce the CMP process cycle time. CMP scrap reduction by overpolish, re-work rate reduction, thickness control efficiency also can be easily achieved. CMP Equipment manufacturer also trying to develop integrated system which has multi-head & platen, cleaner, pre & post thickness measure and even control the polish time from the calculated removal rate of each polishing head by software. CMP re-work problem such as over & under polish by target thickness may result in the cycle time delay. By reducing those inefficient factors during the process and establish of the automatic process control, CLC system need to be adopted to maximize the process performance. Wafer to Wafer Polish Time Feed Back Control by measuring the wafer right after the polish shorten the polish time calculation for the next wafer and it lead to the perfect Post CMP target thickness control capability. By Monitoring all of the processed the wafer, CMP process will also be stabilize itself.

• 한국전기전자재료학회논문지
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• 제16권6호
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• pp.465-470
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• 2003

The chemical mechanical polishing (CMP) process has been widely used for the global planarization of multi-layer structures in semiconductor manufacturing. The CMP process can be optimized by several parameters such as equipment, consumables (pad, backing film and slurry), process variables and post-CMP cleaning. However, the COO(cost of ownership) is very high, because of high consumable cost. Especially, among the consumables, the slurry dominates more than 40 %. In this paper, we have studied the CMP characteristics of diluted silica slurry by adding of raw alumina abrasives and annealed alumina abrasives. As an experimental result, we obtained the comparable slurry characteristics compared with original silica slurry in the view-point of high removal rate and low non-uniformity. Therefore, we can reduce the cost of consumables(COC) of CMP process for ULSI applications.

• 한국전기전자재료학회논문지
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• 제14권1호
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• pp.1-5
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• 2001

STI(shallow trench isolation)-CMP(chemical mechanical polishing) process have been substituted for LOCOS(local oxidation of silicon) process to obtain global planarization in the below sub-0.5㎛ technology. However TI-CMP process, especially TI-CMP with RIE(reactive ion etching) etch back process, has some kinds of defect like nitride residue, torn oxide defect, etc. In this paper, we studied how to reduced torn oxide defects after STI-CMP with RIE etch back processed. Although torn oxide defects which can occur on trench area is not deep and not severe, torn oxide defects on moat area is not deep and not severe, torn oxide defects on moat area is sometimes very deep and makes the yield loss. Thus, we did test on pattern wafers which go through trench process, APECVD process, and RIE etch back process by using an IPEC 472 polisher, IC1000/SUVA4 PAD and KOH base slurry to reduce the number of torn defects and to study what is the origin of torn oxide defects.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.376-377
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• 2006

Chemical Mechanical Planarization (CMP) has emerged as an enabling technology for the manufacturing of multi-level metal interconnects used in high-density Integrated Circuits (IC). Recently, multi-level structures have been also widely used m the MEMS device such as micro engines, pressure sensors, micromechanical fluid pumps, micro mirrors and micro lenses. Especially, among the thin films available in IC technologies, polysilicon has probably found the widest range of uses in silicon technology based MEMS. This paper presents the characteristic of polysilicon CMP for multi-level MEMS structures. Two-step CMP process verifies that is possible to decrease dishing amount with two type of slurries characteristics. This approach is attractive because two-step CMP process can be decreased dishing amount considerably more then just one CMP process.