• 한국빅데이터학회지
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• 제4권2호
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• pp.61-71
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• 2019

반도체 웨이퍼의 표면을 연마하여 평탄화하는 Chemical Mechanical Planarization(CMP) 공정은 다양한 화학물질과 물리적인 기계장치에 의한 작용을 받기 때문에 공정을 안정적으로 관리하기 힘들다. CMP 공정에서 품질 지표로는 Material Removal Rate(MRR)를 많이 사용하고, CMP 공정의 안정적 관리를 위해서는 MRR을 예측하는 것이 중요하다. 본 연구에서는 머신러닝 기법들을 이용하여 CMP 공정에서 수집된 시계열 센서 데이터를 분석하여 MRR을 예측하는 모형과 공정 품질을 해석하기 위한 분류 모형을 개발한다. 나아가 분류 결과를 분석하여, CMP 공정 품질에 영향을 미치는 유의미한 변수를 파악하고 고품질을 유지하기 위한 공정 조건을 설명한다.

• 마이크로전자및패키징학회지
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• 제9권4호
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• pp.17-23
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• 2002

최근 반도체 소자의 고속화 및 고집적화에 따라 배선 패턴이 미세화 되고 다층의 금속 배선 공정이 요구됨에 따라 단차를 줄이고 표면을 광역 평탄화 시킬 수 있는 STI-CMP 공정이 도입되었다. 그러나, STI-CMP 공정이 다소 복잡해짐에 따라 질화막 잔존물, 찢겨진 산화막 결함들과 같은 여러 가지 공정상의 문제점들이 심각하게 증가하고 있다. 본 논문에서는 이상과 같은 CMP 공정 결함들을 줄이고, STI-CMP 공정의 최적 조건을 확보하기 위해 트렌치 깊이와 STI-fill 산화막 두께가 리버스 모트 식각 공정 후, 트랜치 위의 예리한 산화막의 취약함과 STI-CMP공정 후의 질화막 잔존물 등과 같은 결함들에 미치는 영향에 대해 연구하였다. 실험결과, CMP 공정에서 STI-fill의 두께가 얇을수록, 트랜치 깊이가 깊을수록 찢겨진 산화막의 발생이 증가하였다. 트랜치 깊이가 낮고 CMP 두께가 높으면 질화막 잔존물이 늘어나는 반면, 트랜치 깊이가 깊어 과도한 연마가 진행되면 활성영역의 실리콘 손상을 받음을 알 수 있었다

• Tribology and Lubricants
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• 제31권6호
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• pp.239-244
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• 2015

Chemical mechanical polishing (CMP) is one of the most important processes for enabling sub-14 nm semiconductor manufacturing. Moreover, post-CMP defect control is a key process parameter for the purpose of yield enhancement and device reliability. Due to the complexity of device with sub-14 nm node structure, CMP-induced defects need to be fixed in the CMP in-situ cleaning module instead of during post ex-situ wet cleaning. Therefore, post-CMP in-situ cleaning optimization and cleaning efficiency improvement play a pivotal role in post-CMP defect control. CMP in-situ cleaning module normally consists of megasonic and brush scrubber processes. And there has been an increasing effort for the optimization of cleaning chemistry and brush scrubber cleaning in the CMP cleaning module. Although there have been many studies conducted on improving particle removal efficiency by brush cleaning, these studies do not consider the effects of brush contamination. Depending on the process condition and brush condition, brush cross contamination effects significantly influence post-CMP cleaning defects. This study investigates brush cross contamination effects in the CMP in-situ cleaning module by conducting experiments using 300mm tetraethyl orthosilicate (TEOS) blanket wafers. This study also explores brush pre-treatment in the CMP tool and proposes recipe effects, and critical process parameters for optimized CMP in-situ cleaning process through experimental results.

• Tribology and Lubricants
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• 제34권3호
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• pp.115-122
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• 2018

Chemical mechanical polishing (CMP) is a hybrid processing method in which the surface of a wafer is planarized by chemical and mechanical material removal. Since mechanical material removal in CMP is caused by the rolling or sliding of abrasive particles, interfacial friction during processing greatly influences the CMP results. In this paper, the trend of tribology research on CMP process is discussed. First, various friction force monitoring methods are introduced, and three elements in the CMP tribo-system are defined based on the material removal mechanism of the CMP process. Tribological studies on the CMP process include studies of interfacial friction due to changes in consumables such as slurry and polishing pad, modeling of material removal rate using contact mechanics, and stick-slip friction and scratches. The real area of contact (RCA) between the polishing pad and wafer also has a significant influence on the polishing result in the CMP process, and many researchers have studied RCA control and prediction. Despite the fact that the CMP process is a hybrid process using chemical reactions and mechanical material removal, tribological studies to date have yet to clarify the effects of chemical reactions on interfacial friction. In addition, it is necessary to clarify the relationship between the interface friction phenomenon and physical surface defects in CMP, and the cause of their occurrence.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 춘계학술대회 논문집 유기절연재료 전자세라믹 방전플라즈마 일렉트렛트 및 응용기술
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• pp.223-227
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• 2002

As the channel length of device shrinks below $0.13{\mu}m$, CMP(chemical mechanical polishing) process got into key process for global planarization in the chip manufacturing process. The removal rate and non-uniformity of the CMP characteristics occupy an important position to CMP process control. Especially, the post-CMP thickness variation depends on the device yield as well as the stability of subsequent process. In this paper, every wafer polished two times for the improvement of oxide CMP process characteristics. Then, we discussed the removal rate and non-uniformity characteristics of post-CMP process. As a result of CMP experiment, we have obtained within-wafer non-uniformity (WIWNU) below 4 [%], and wafer-to-wafer non-uniformity (WTWNU) within 3.5 [%]. It is very good result, because the reliable non-uniformity of CMP process is within 5 [%].

• Transactions on Electrical and Electronic Materials
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• 제3권4호
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• pp.5-9
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• 2002

Chemical mechanical polishing (CMP) has become the preferred planarization method for multilevel interconnect technology due to its ability to achieve a high degree of feature level planarity. Especially, to achieve the higher density and greater performance, shallow trench isolation (STI)-CMP process has been attracted attention for multilevel interconnection as an essential isolation technology. Also, it was possible to apply the direct STI-CMP process without reverse moat etch step using high selectivity slurry (HSS). In this work, we determined the process margin with optimized process conditions to apply HSS STI-CMP process. Then, we evaluated the reliability and reproducibility of STI-CMP process through the optimal process conditions. The wafer-to-wafer thickness variation and day-by-day reproducibility of STI-CMP process after repeatable tests were investigated. Our experimental results show, quite acceptable and reproducible CMP results with a wafer-to-wafer thickness variation within 400$\AA$.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.90-93
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• 2000

In this study, the rise throughput and the stability in fabrication of device can be obtained by applying of CMP process to STI structure in 0.18um semiconductor device. To employ in STI CMP, the reverse moat process has been added thus the process became complex and the defects were seriously increased. Removal rates of each thin films in STI CMP was not equal hence the devices must to be effected, that is, the damage was occured in the device dimension in the case of excessive CMP process and the nitride film was remained on the device dimension in the case of insufficient CMP process than these defects affect the device characteristics. To resolve these problems, the development of slurry for CMP with high removal rate and high selectivity between each thin films was studied then it can be prevent the reasons of many defects by reasons of many defects by simplification of process that directly apply CMP process to STI structure without the reverse moat pattern process.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.354-355
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• 2005

Indium tin oxide (ITO) thin film was polished by chemical mechanical polishing (CMP) by the change of process parameters for the improvement of electrical and optical properties of ITO thin film. Light transparent efficiency of ITO thin film was improved after CMP process at the optimized process parameters compared to that before CMP process.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 춘계학술대회 논문집 전자세라믹스 센서 및 박막재료 반도체재료 일렉트렛트 및 응용기술
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• pp.14-17
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• 2000

The rise throughput and the stability in fabrication of device can be obtained by applying of CMP process to STI structure in 0.18um semiconductor device. To employ in STI CMP, the reverse moat process has been added thus the process became complex and the defects were seriously increased. Removal rates of each thin films in STi CMP was not equal hence the devices must to be effected, that is, the damage was occured in the device dimension in the case of excessive CMP process and the nitride film was remained on the device dimension in the case of insufficient CMP process than these defects affect the device characteristics. We studied the current sensing method in STI-CMP with the reverse moat pattern.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집
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• pp.189-192
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• 2001

Recently, STI process is getting attention as a necessary technology for making high density of semiconductor by devices isolation method. However, it does have various problems caused by CMP process, such as torn oxide defects, nitride residues on oxide, damages of si active region, contaminations due to post-CMP cleaning, difficulty of accurate end point detection in CMP process, etc. In this work, the various defects induced by CMP process was introduced and the above mentioned Problems of CMP process was examined in detail. Finally, the guideline of future CMP process was presented to reduce the effects of these defects.