• The Journal of Bigdata
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• v.4 no.2
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• pp.61-71
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• 2019

Chemical Mechanical Planarization (CMP) process that planarizes semiconductor wafer's surface by polishing is difficult to manage reliably since it is under various chemicals and physical machinery. In CMP process, Material Removal Rate (MRR) is often used for a quality indicator, and it is important to predict MRR in managing CMP process stably. In this study, we introduce prediction models using machine learning techniques of analyzing time-series sensor data collected in CMP process, and the classification models that are used to interpret process quality conditions. In addition, we find meaningful variables affecting process quality and explain process variables' conditions to keep process quality high by analyzing classification result.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.4
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• pp.17-23
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• 2002

The more productive and stable fabrication can be obtained by applying chemical mechanical polishing (CMP) process to shallow trench isolation (STI) structure in 0.18 $\mu\textrm{m}$ semiconductor device. However, STI-CMP process became more complex, and some kinds of defect such as nitride residue, tern oxide defect were seriously increased. Defects like nitride residue and silicon damage after STI-CMP process were discussed to accomplish its optimum process condition. In this paper, we studied how to reduce torn oxide defects and nitride residue after STI-CMP process. To understand its optimum process condition, We studied overall STI-related processes including trench depth, STI-fill thickness and post-CMP thickness. As an experimental result showed that as the STI-fill thickness becomes thinner, and trench depth gets deeper, more tern oxide were found in the CMP process. Also, we could conclude that low trench depth whereas high CMP thickness can cause nitride residue, and high trench depth and over-polishing can cause silicon damage.

• Tribology and Lubricants
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• v.31 no.6
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• pp.239-244
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• 2015

Chemical mechanical polishing (CMP) is one of the most important processes for enabling sub-14 nm semiconductor manufacturing. Moreover, post-CMP defect control is a key process parameter for the purpose of yield enhancement and device reliability. Due to the complexity of device with sub-14 nm node structure, CMP-induced defects need to be fixed in the CMP in-situ cleaning module instead of during post ex-situ wet cleaning. Therefore, post-CMP in-situ cleaning optimization and cleaning efficiency improvement play a pivotal role in post-CMP defect control. CMP in-situ cleaning module normally consists of megasonic and brush scrubber processes. And there has been an increasing effort for the optimization of cleaning chemistry and brush scrubber cleaning in the CMP cleaning module. Although there have been many studies conducted on improving particle removal efficiency by brush cleaning, these studies do not consider the effects of brush contamination. Depending on the process condition and brush condition, brush cross contamination effects significantly influence post-CMP cleaning defects. This study investigates brush cross contamination effects in the CMP in-situ cleaning module by conducting experiments using 300mm tetraethyl orthosilicate (TEOS) blanket wafers. This study also explores brush pre-treatment in the CMP tool and proposes recipe effects, and critical process parameters for optimized CMP in-situ cleaning process through experimental results.

• Tribology and Lubricants
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• v.34 no.3
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• pp.115-122
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• 2018

Chemical mechanical polishing (CMP) is a hybrid processing method in which the surface of a wafer is planarized by chemical and mechanical material removal. Since mechanical material removal in CMP is caused by the rolling or sliding of abrasive particles, interfacial friction during processing greatly influences the CMP results. In this paper, the trend of tribology research on CMP process is discussed. First, various friction force monitoring methods are introduced, and three elements in the CMP tribo-system are defined based on the material removal mechanism of the CMP process. Tribological studies on the CMP process include studies of interfacial friction due to changes in consumables such as slurry and polishing pad, modeling of material removal rate using contact mechanics, and stick-slip friction and scratches. The real area of contact (RCA) between the polishing pad and wafer also has a significant influence on the polishing result in the CMP process, and many researchers have studied RCA control and prediction. Despite the fact that the CMP process is a hybrid process using chemical reactions and mechanical material removal, tribological studies to date have yet to clarify the effects of chemical reactions on interfacial friction. In addition, it is necessary to clarify the relationship between the interface friction phenomenon and physical surface defects in CMP, and the cause of their occurrence.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05c
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• pp.223-227
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• 2002

As the channel length of device shrinks below $0.13{\mu}m$, CMP(chemical mechanical polishing) process got into key process for global planarization in the chip manufacturing process. The removal rate and non-uniformity of the CMP characteristics occupy an important position to CMP process control. Especially, the post-CMP thickness variation depends on the device yield as well as the stability of subsequent process. In this paper, every wafer polished two times for the improvement of oxide CMP process characteristics. Then, we discussed the removal rate and non-uniformity characteristics of post-CMP process. As a result of CMP experiment, we have obtained within-wafer non-uniformity (WIWNU) below 4 [%], and wafer-to-wafer non-uniformity (WTWNU) within 3.5 [%]. It is very good result, because the reliable non-uniformity of CMP process is within 5 [%].

• Transactions on Electrical and Electronic Materials
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• v.3 no.4
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• pp.5-9
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• 2002

Chemical mechanical polishing (CMP) has become the preferred planarization method for multilevel interconnect technology due to its ability to achieve a high degree of feature level planarity. Especially, to achieve the higher density and greater performance, shallow trench isolation (STI)-CMP process has been attracted attention for multilevel interconnection as an essential isolation technology. Also, it was possible to apply the direct STI-CMP process without reverse moat etch step using high selectivity slurry (HSS). In this work, we determined the process margin with optimized process conditions to apply HSS STI-CMP process. Then, we evaluated the reliability and reproducibility of STI-CMP process through the optimal process conditions. The wafer-to-wafer thickness variation and day-by-day reproducibility of STI-CMP process after repeatable tests were investigated. Our experimental results show, quite acceptable and reproducible CMP results with a wafer-to-wafer thickness variation within 400$\AA$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.90-93
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• 2000

In this study, the rise throughput and the stability in fabrication of device can be obtained by applying of CMP process to STI structure in 0.18um semiconductor device. To employ in STI CMP, the reverse moat process has been added thus the process became complex and the defects were seriously increased. Removal rates of each thin films in STI CMP was not equal hence the devices must to be effected, that is, the damage was occured in the device dimension in the case of excessive CMP process and the nitride film was remained on the device dimension in the case of insufficient CMP process than these defects affect the device characteristics. To resolve these problems, the development of slurry for CMP with high removal rate and high selectivity between each thin films was studied then it can be prevent the reasons of many defects by reasons of many defects by simplification of process that directly apply CMP process to STI structure without the reverse moat pattern process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.354-355
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• 2005

Indium tin oxide (ITO) thin film was polished by chemical mechanical polishing (CMP) by the change of process parameters for the improvement of electrical and optical properties of ITO thin film. Light transparent efficiency of ITO thin film was improved after CMP process at the optimized process parameters compared to that before CMP process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.14-17
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• 2000

The rise throughput and the stability in fabrication of device can be obtained by applying of CMP process to STI structure in 0.18um semiconductor device. To employ in STI CMP, the reverse moat process has been added thus the process became complex and the defects were seriously increased. Removal rates of each thin films in STi CMP was not equal hence the devices must to be effected, that is, the damage was occured in the device dimension in the case of excessive CMP process and the nitride film was remained on the device dimension in the case of insufficient CMP process than these defects affect the device characteristics. We studied the current sensing method in STI-CMP with the reverse moat pattern.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.189-192
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• 2001

Recently, STI process is getting attention as a necessary technology for making high density of semiconductor by devices isolation method. However, it does have various problems caused by CMP process, such as torn oxide defects, nitride residues on oxide, damages of si active region, contaminations due to post-CMP cleaning, difficulty of accurate end point detection in CMP process, etc. In this work, the various defects induced by CMP process was introduced and the above mentioned Problems of CMP process was examined in detail. Finally, the guideline of future CMP process was presented to reduce the effects of these defects.