• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.101-102
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• 2006

PZT thin films, which are the representative ferroelectric materials in ferroelectric random access memory (FRAM), have some serious problem such as the imprint, retention and fatigue which ferroelectric properties are degraded by repetitive polarization. BL T thin film capacitors were fabricated by plasma etching, however, the plasma etching of BLT thin film was known to be very difficult. In our previous study, the ferroelectric materials such as PZT and BLT were patterned by chemical mechanical polishing (CMP) using damascene process to top electrode/ferroelectric material/bottom electrode. It is also possible to pattern the BLT thin film capacitors by CMP, however, the CMP damage was not considered in the experiments. The properties of BLT thin films were changed by the change of polishing pressure although the removal rate was directly proportional to the polishing pressure in CMP process.

• Journal of the KSME
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• v.56 no.7
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• pp.36-39
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• 2016

이 글에서는 1G DR AM급 이상의 고집적 반도체 소자를 제조하기 위해 필수적인 표면 평탄화 방법으로 CMP(Chemical Mechanical Planarization) 공정을 소개한다. 특히 반도체 소자를 구성하는 재료의 화학적 반응과 기계적 마멸 정도에 적합한 연마(polishing) 처방을 제공하고자 한다.

• Tribology and Lubricants
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• v.34 no.6
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• pp.279-283
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• 2018

In this study, we investigate the behavior of abrasive particles and change of the stick-slip pattern according to chemical mechanical polishing (CMP) process parameters when a large number of abrasive particles are fixed on a pad. The CMP process is simulated using the finite element method. In the simulation, the abrasive grains are composed of those used in the actual CMP process. Considering the cohesion of the abrasive grains with the start of the CMP process, abrasive particles with various sizes are fixed onto the pad at different intervals so that stick-slip could occur. In this analysis, we determine that when the abrasive particle size is relatively large, the stick-slip period does not change as the pressure increases while the moving speed is constant. However, if the size of the abrasive grains is relatively small, the amount of deformation of the grains increases due to the elasticity of the pad. Therefore, the stick-slip pattern may not be observed. As the number of abrasive particles increases, the stick-slip period and displacement decrease. This is consistent with the decrease in the von Mises yield stress value on the surface of the wafer as the number of abrasive grains increases. We determine that when the number of the abrasive grains increases, the polishing rate, and characteristics are improved, and scratches are reduced. Moreover, we establish that the period of stick-slip increases and the change of the stick-slip size was not large when the abrasive particle size was relatively small.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.10a
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• pp.24.2-24.2
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• 2011

Ru is used as a bottom electrode capacitor in dynamic random access memories (DRAMs) and ferroelectric random access memories (FRAMs). The surface of the Ru needs to be planarized which is usually done by chemical mechanical polishing (CMP). Ru CMP process requires chemical slurry consisting of abrasive particles and oxidizer. A slurry containing NaIO4 and alumina particles is already proposed for Ru CMP process. However, the stability of the slurry is critical in the CMP process since if the particles in the slurry get agglomerated it would leave scratches on the surface being planarized. Thus, in the present work, the stability behavior of the slurry using a suitable anionic polyelectrolyte is investigated. The parameters such as slurry pH, polyelectrolyte concentration, adsorption time and the sequence of addition of chemicals are optimized. The results show that the slurry is stable for longer time at an optimized condition. The polishing behavior of the Ru using the optimized slurry is also investigated.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.6
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• pp.1146-1150
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• 2009

Cadmium telluride (CdTe) is one of the most attractive photovoltaic materials due to its low cost, high efficiency and stable performance in physical, optical and electronic properties. Few researches on the influences of uniform surface on the photovoltaic characteristics in large-area CdTe solar cell were not reported. As the preceding study of the effects of thickness-uniformity on the photovoltaic characteristics for the large-area CdTe thin film solar cell, chemical mechanical polishing (CMP) process was investigated for an enhancement of thickness-uniformity. Removal rate of CdTe thin film was 3160 nm/min of the maximum value at the 200 $gf/cm^2$ of down force (pressure) and 60 rpm of table speed (velocity). The removal rate of CdTe thin film was more affected by the down force than the table speed which is the two main factors directly influencing on the removal rate in CMP process. RMS roughness and peak-to-valley roughness of CdTe thin film after CMP process were improved to 96.68% and 85.55%, respectively. The optimum process condition was estimated by 100 $gf/cm^2$ of down force and 60 rpm of table speed with the consideration of good removal uniformity about 5.0% as well as excellent surface roughness for the large-area CdTe solar cell.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.55-56
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• 2006

In this paper, we first applied the chemical mechanical polishing (CMP) process to the planarization of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interface. BST ($Ba_{0.6}Sr_{0.4}TiO_3$), PZT ($Pb_{1.1}(Zr_{0.52}TiO_{0.48})O_3$) and BTO ($BaTiO_3$) ferroelectric film are fabricated by the sol-gel method. And then, we compared the structural characteristics before and after CMP process of BST, PZT, BTO films. Their dependence on slurry composition was also investigated. We expect that our results will be useful promise of global planarization for ferroelectric random access memories (FRAM) application in the near future.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.66-66
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• 2007

Lead zirconate titanate (PZT) is one of the most attractive perovskite-type materials for ferroelectric random access memory (FRAM) due to its higher remanant polarization and the ability to withstand higher coercive fields. We first applied the damascene process using chemical mechanical polishing (CMP) to fabricate the PZT thin film capacitor to solve the problems of plasma etching including low etching profile and ion charging. The $0.8{\times}0.8\;{\mu}m$ square patterns of silicon dioxide on Pt/Ti/$SiO_2$/Si substrate were coated by sol-gel method with the precursor solution of PZT. Damascene process by CMP was performed to pattern the PZT thin film with the vertical sidewall and no plasma damage. The polarization-voltage (P-V) characteristics of PZT capacitors and the current-voltage characteristics (I-V) were examined by change of process parameters. To examine the CMP induced damage to PZT capacitor, the domain structure of the polished PZT thin film was also investigated by piezoresponse force microscopy (PFM).

• Journal of the Korean Society for Precision Engineering
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• v.19 no.5
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• pp.149-158
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• 2002

Recently, the minimum line width shows a tendency to decrease and the multi-level increases in semiconductor. Therefore, a planarization technique is needed and chemical mechanical polishing(CMP) is considered as one of the most suitable process. CMP accomplishes a high polishing performance and a global planarization of high quality. However there are several defects in CMF, such as micro-scratches, abrasive contaminations and non-uniformity of polished wafer edges. Wet etching process including spin-etching can eliminate the defects of CMP. It uses abrasive-free chemical solution instead of slurry. On this study, ILD(Interlayer-Dielectric) was removed by CMP and wet etching process using DHF(Diluted HF) in order to investigate the possibility of planrization by wet etching mechanism. In the thin film wafer, the results were evaluated from the viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU). And the pattern step heights were also compared for the purpose of planarity characterization of the patterned wafer. Moreover, Chemical polishing process which is the wet etching process with mechanical energy was introduced and evaluated for examining the characteristics of planarization.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.569-570
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• 2006

The conditioning process is very important process for the CMP (Chemical Mechaning Polishing). This process regenerates the roughness of the polishing pad during the CMP process, increases the MRR (Material Removal Rate) and gives us longer pad life so conditioning process is essential for the CMP, and conditioning process influences the polishing pad shape gradually. Conditining process is related to the Non-Uniformity. In This paper, Kinematic of the conditioning process and mathematic modeling of the pad wear is studied and result shows how the various parameters influence the pad shape and WIWNU[1]. Consequently through these parameter, optimal design of the conditioning process equipment is predicted.

• Journal of the Korean Society for Precision Engineering
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• v.19 no.6
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• pp.145-154
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• 2002

CMP (Chemical mechanical polishing) process was used to control the fine grinding process induced mechanical damage of Cz Silicon wafer. Characterization of mechanical damage was carried out using Nomarski microscope, magic mirror and also using angle lapping and lifetime scanner evaluation after heat treatment. Magic mirror and lifetime scanner were very useful for the residual damage pattern characterization and CMP process was effective on the reduction of fine grinding induced mechanical damage.