• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.71-78
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• 2012

This paper describes trends in conventional scaling compared with advanced technologies such as 3D integration (3DI) and bumpless through-silicon via (TSV) processes, as well as the characteristics of CMOS (Complementary Metal Oxide Semiconductor) Logic device after thinning the wafers to less than $10{\mu}m$. Each module process including thinning, stacking, and TSV, is optimized for 3D Wafer-on-Wafer (WOW) application. Optimization results are discussed with valuable data in detail. Since vertical wiring of bumpless TSV can be connected directly to the upper and lower substrates by self-alignment, bumps are not necessary when TSV interconnects are used.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.67-74
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• 2000

In this paper, a $54{\times}54$-bit multiplier based on a improved conditional sum adder is proposed. To reduce the multiplication time, high compression-rate compressors without Booth's Encoding, and a 108-bit conditional sum adder with separated carry generation block, are developed. Furthermore, a design technique based on pass-transistor logic is utilized for optimize the multiplication time and the power consumption by about 5% compared to that of conventional one. With $0.65{\mu}m$, single-poly, triple-metal CMOS process, its chip size is $6.60{\times}6.69\;mm^2$ and the multiplication time is 135.ns at a 3.3V power supply.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.2
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• pp.50-55
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• 2001

In this paper, a 8bit parity checker/generator is designed using a new gate which is proposed to implement the exclusive or(XOR) and exclusive-nor(XNOR) functions for low power consumption on transistor level. Conventional XOR/XNOR gate such as CPL, DPL and CCPL designed to reduce the power consumption has an inverter to get the full swing output signals. But this inverter consumes the major part of power and causes the time delay on CMOS circuits. Thus a new technique was adopted not utilizing inverter in the circuits. The results of simulation by Hspice shows 33% of power reduction compared with CCPL gate when A 8 bit parity checker was made with the proposed new gate using $0.8{\mu}mCMOS$ technology.

• Journal of Sensor Science and Technology
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• v.18 no.4
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• pp.274-279
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• 2009

In this paper, a wide dynamic range active pixel sensor(APS) with output voltage feedback structure has been designed by a 2-poly 4-metal 0.35 $\mu$m standard CMOS technology. We presented a novel APS with output voltage feedback, which exhibits a wide dynamic range. The dynamic range increases at the cost of an additional diode and an additional MOSFET. The output voltage feedback structure enables the control of the output voltage level by itself, as incident light power varies. It is confirmed that the light level which the output voltage level of proposed APS is saturated is about 120,000 lux, which is higher than that of a conventional 3-transistor APS.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.1-12
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• 2001

Based on mixed-mode transient analyses utilizing a 2-dimensional device simulator, we have suggested the methodology to analyze the HBM ESD phenomena in CMOS chips utilizing NMOS transistors for ESD protection, and have analyzes the HBM discharge mechanisms in detail. Also the second breakdown characteristics in the protection device have been successfully simulated based on mixed-mode simulations, to explain the discharge mechanisms leading to device failure. To analyze the effects of the device structure changes on the discharge characteristics, we have compared the results of DC analyses and mixed-mode transient analyses, and have discussed about more robust designs of NMOS transistor structures against HBM ESD based on the analyses.

• The KIPS Transactions:PartA
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• v.14A no.3 s.107
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• pp.147-150
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• 2007

This paper describes a new low-swing inverter for low power consumption. To reduce a power consumption, an output voltage swing is in the range from 0 to VDD-2VTH. This can be done by the inverter structure that allow a full swing or a swing on its input terminal without leakage current. Using this low-swing voltage technology, we proposed a low-power 16$\times$16 bit parallel multiplier. The proposed circuits are designed with Samsung 0.35$\mu$m standard CMOS process at a 3.3V supply voltage. The validity and effectiveness are verified through the HSPICE simulation.. Compared to the previous works, this circuit can reduce the power consumption rate of 17.3% and the power-delay product of 16.5%.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.1
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• pp.43-47
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• 2024

The size of semiconductor devices has been scaled down to improve packing density and output performance. However, there is uncontrollable spreading of the dopants that comprise the well, punch-stop, and channel-stop when using high-temperature annealing processes, such as rapid thermal annealing (RTA). In this context, low-temperature deuterium annealing (LTDA) performed at a low temperature of 300℃ is proposed to reduce the thermal budget during CMOS fabrication. The LTDA effectively eliminates the interface trap in the gate dielectric layer, thereby improving the electrical characteristics of devices, such as threshold voltage (V_TH), subthreshold swing (SS), on-state current (I_ON), and off-state current (I_OFF). Moreover, the LTDA is perfectly compatible with CMOS processes.

• Journal of Korea Society of Digital Industry and Information Management
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• v.20 no.2
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• pp.63-74
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• 2024

This Paper presents a resistive wideband fully differential low-noise amplifier (LNA) designed using a noise-cancellation technique for TV tuner applications. The front-end of the LNA employs a cascode common-gate (CG) configuration, and cross-coupled local feedback is employed between the CG and common-source (CS) stages. The moderate gain at the source of the cascode transistor in the CS stage is utilized to boost the transconductance of the cascode CG stage. This produces higher gain and lower noise figure (NF) than a conventional LNA with inductor. The NF can be further optimized by adjusting the local open-loop gain, thereby distributing the power consumption among the transistors and resistors. Finally, an optimized DC gain is obtained by designing the output resistive network. The proposed LNA, designed in SK Hynix 180 nm CMOS, exhibits improved linearity with a voltage gain of 10.7 dB, and minimum NF of 1.6-1.9 dB over a signal bandwidth of 40 MHz to 1 GHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.451-454
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• 2015

This paper introduces 3 type of OTAs with $0.35-{\mu}m$ standard CMOS technology for Low-Power, Low-Voltage. The first type is a two-stage OTA designed to operate with a 1-V VDD and it has $1.774{\mu}W$ low power consumption. All transistors are operating in strong inversion. It takes Gm-Enhancement techniques to compensate gm, which is lowered by Bulk-Driven technique and has an Wide swing current mirror for low voltage operation and a Class-A output. The second type is a Two-stage OTA designed to operate with a 0.8-V VDD and It has 52nW low power consumption and 112dB high gain. The current mirror uses Composite Transistor binding Gates of two MOSFET to raise Rout which is similar with cascode structure. The third type is a Two-stage OTA designed to operate with a 0.6-V VDD and It has 160nW low power consumption and 72dB high gain. It takes Level Shift technique by Common Gate structure to amplify signals without additional bias voltage at second stage.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.509-518
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• 2023

In this paper, we designed a 4Kb poly-fuse OTP IP (Intellectual Property) required for analog circuit trimming and calibration. In order to reduce the BL resistance of the poly-fuse OTP cell, which consists of an NMOS select transistor and a poly-fuse link, the BL stacked metal 2 and metal 3. In order to reduce BL routing resistance, the 4Kb cells are divided into two sub-block cell arrays of 64 rows × 32 rows, with the BL drive circuit located between the two 2Kb sub-block cell arrays, which are split into top and bottom. On the other hand, in this paper, we propose a core circuit for an OTP cell that uses one poly-fuse link to one select transistor. In addition, in the early stages of OTP IP development, we proposed a data sensing circuit that considers the case where the resistance of the unprogrammed poly-fuse can be up to 5kΩ. It also reduces the current flowing through an unprogrammed poly-fuse link in read mode to 138㎂ or less. The poly-fuse OTP cell size designed with DB HiTek 90nm CMOS process is 11.43㎛ × 2.88㎛ (=32.9184㎛2), and the 4Kb poly-fuse OTP IP size is 432.442㎛ × 524.6㎛ (=0.227mm²).