• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.50-56
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• 2008

In this paper, we propose a partial access mechanism for low cost multimedia processors. Due to the cost increase of adding the SIMD register files and the execution blocks, we experience difficulties applying the SIMD instructions to low cost multimedia embedded processors. The proposed mechanism has the advantages of decreasing the cost burden of the additional hardware and enhancing total performance of the SIMD operation. We designed the ASIP in which the mechanism is applied and compared the latency of the SIMD operation regarding the use of instruction sets in the DSP benchmark. Then, we analyzed the total performance enhancement and the reduction in area burden by synthesizing the ASIP using 0.25um TSMC CMOS technology. As a result, there are approximately a 38% of performance increase and a 13.4% of area increase according to the proposed mechanism simulation.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.7-10
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• 2003

Samsung SDI has developed a full color 5.0" WVGA AMOLED display with top emission and a super fine pitch of 0.1365mm(l86ppi), the world's highest resolution OLED display ever reported to date. Scan driver circuits and demux circuit were integrated into the display panel, using low temperature poly-Si TFT CMOS technology, and data driver circuit were mounted using COG chips. Peak luminescence was greater than 300cd/ $m^2$ with power consumption of 500mW with 30% of the pixels on illuminated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.89-95
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• 2008

In this paper, we designed a low power face detection hardware and analysed its power consumption. The face detection hardware was fabricated using Samsung 0.18um CMOS technology and it can detect multiple face locations from a 2-D image. The hardware is composed of 6 functional modules and 11 internal memories. We introduced two operating modes(SLEEP and ACTIVE) to save power and a clock gating technique was used at two different levels: modules and registers. In additional, we divided an internal memory into several pieces to reduce the energy consumed when accessing memories, and fully utilized low power design option provided in Synopsis Design Compiler. As a result, we could obtain 68% power reduction in ACTIVE mode compared to the original design in which none of the above low power techniques were used.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.9
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• pp.798-805
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• 2015

This paper proposes Relaxation Oscillator with Random Number Generator to minimize electromagnetic interference (EMI) noise. DC-DC Converter with Relaxation Oscillator is presented how much spurious noise effects to RF Receiver system. The main frequency of the proposed Relaxation oscillator is 7.9 MHz to operate it and add temperature compensation block to be applied to the frequency compensation in response to temperature changes. The DC-DC Converter Spurious noise is reduced up to 20 dB through changing frequency randomly. It is fabricated in $0.18{\mu}m$ CMOS technology. The active area occupies an area of $220{\mu}m{\times}280{\mu}m$. The supply voltage is 1.8 V and current consumption is $500{\mu}A$.

• Journal of IKEEE
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• v.10 no.1 s.18
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• pp.10-15
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• 2006

In this paper, a clock and data recovery (CDR) circuit for a serial link with a half rate 4x oversampling phase and frequency detector structure without a reference clock is described. The phase detector (PD) and frequency detector (FD)are designed by 4X oversampling method. The PD, which uses bang-bang method, finds the phase error by generating four up/down signal and the FD, which uses the rotational method, finds the frequency error by generating up/down signal made by the PD output. And the six signals of the PD and the FD control an amount of current that flows through the charge pump. The VCO composed of four differential buffer stages generates eight differential clocks. Proposed circuit is designed using the 0.18um CMOS technology and operating voltage is 1.8V. With a 4X oversampling PD and FD technique, tracking range of 24% at 3.125Gbps is achieved.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.31-43
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• 1999

The main goal of this paper is to design a high performance SVP(Stack based Video Processor) for network applications. The SVP is a comprehensive scheme; 'better' in the sense that it is an optimal selection of previously proposed enhancements of a stack machine and a video processor. This can process effectively object-based video data using a S-RISC(Stack-based Reduced Instruction Set Computer) with a semi -general-purpose architecture having a stack buffer for OOP(Object-Oriented Programming) with many small procedures at running programs. And it includes a vector processor that can improve the MPEG coding speed. The vector processor in the SVP can execute advanced mode motion compensation, motion prediction by half pixel and SA-DCT(Shape Adaptive-Discrete Cosine Transform) of MPEG-4. Absolutors and halfers in the vector processor make this architecture extensive to a encoder. We also designed a VLSI stack-oriented video processor using the proposed architecture of stack-oriented video decoding. It was designed with O.5$\mu\textrm{m}$ 3LM standard-cell technology, and has 110K logic gates and 12 Kbits SRAM internal buffer. The operating frequency is 50MHz. This executes algorithms of video decoding for QCIF 15fps(frame per second), maximum rate of VLBV(Very Low Bitrate Video) in MPEG-4.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.75-81
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• 2015

This paper proposed the new eight-parallel MDC FFT processor using the eight-parallel MDC architecture and the efficient scheduling scheme. The proposed FFT processor supports the 256-point FFT based on the modified radix-$2^6$ FFT algorithm. The proposed scheduling scheme can reduce the number of complex multipliers from eight to six without increasing delay buffers and computation cycles. Moreover, the proposed FFT processor can be used in OFDM systems required high throughput and low hardware complexity. The proposed FFT processor has been designed and implemented with a 90nm CMOS technology. The experimental result shows that the area of the proposed FFT processor is $0.27mm^2$. Furthermore, the proposed eight-parallel MDC FFT processor can achieve the throughput rate up to 2.7 GSample/s at 388MHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.7
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• pp.29-35
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• 2017

This paper presents a high-throughput area-efficient mixed-radix fast Fourier transform (FFT) processor using the efficient scheduling schemes. The proposed FFT processor can support 64, 128, 256, and 512-point FFTs for orthogonal frequency division multiplexing (OFDM) systems, and can achieve a high throughput using mixed-radix algorithm and eight-parallel multipath delay commutator (MDC) architecture. This paper proposes new scheduling schemes to reduce the size of read-only memories (ROMs) and complex constant multipliers without increasing delay elements and computation cycles; thus, reducing the hardware complexity further. The proposed mixed-radix MDC FFT processor is designed and implemented using the Samsung 65nm complementary metal-oxide semiconductor (CMOS) technology. The experimental result shows that the area of the proposed FFT processor is 0.36 mm2. Furthermore, the proposed processor can achieve high throughput rates of up to 2.64 GSample/s at 330 MHz.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.7
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• pp.665-670
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• 2016

In this paper, we suggest the design of OP-AMP using MOSFET in the operation of sub-threshold condition as a basic unit of an IoT. The sub-threshold operation of MOSFET is useful for an ultra low power consumption of sensor network system in the IoT, because it cause the supply voltage to be reduced. From the simulation result using 0.35 um CMOS process, the supply voltage, VDD can be reduced with 0.6 V, open-loop gain of 43 dB and the power consumption was evaluated with about $1.3{\mu}W$ and the active size for an integration was measured with $64{\mu}m{\times}105{\mu}m$. It is expected that the proposed circuit is applied to the low power sensor network for IoT.

• Proceedings of the KIPE Conference
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• 2003.11a
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• pp.214-217
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• 2003

The connectorless power supply system on that multi-contact causes confidence when the wiring reconstructed in the rear. As you see above, contact points between sets and indoor space cause inferior function of audio frequency so it needs to be eliminated. This paper explains the structure of connectorless power supply to supply the system with power crossing the air gap in the part of inductively in the connectorless power supply of both magnetic and electrical model. To get maximum output of electrical load, compensating capacitor compensates to show inter-inductance, lequeage-inductance reducing the track-inductance and access the conditions for resonance. At that time it accesses the maximum electric power. The small change of the value of compensating capacitor causes the changes of maximum electric power. Here the power electronics technology is used not only in the industrial machinery but also in the home appliances so the switching power supply is used to actualize the miniaturization, lightweight, and high efficiency. Generally the condenser input methods are widely used in the rectification circuit of switching power supply, but condenser input method generate great quantity of high frequency components because with this method the current flows in the power input filtering condenser only around value of peak of ac input voltage. To solve these problems, installation of power factor improve circuit on the front of filtering capacitence was considered. Several methods were suggested regarding, but the active filter method which makes smalliging and highly power factor possible are the produce main stream. IC for power factor improvement can be utilized by CMOS process proposing low power consumption. When the high power factor is considered seriously in the power factor improvement circuit, active filter method is selected. In the active filter method, the boost converter is used. Regarding this ·the boost converter is needed.